AXW23 User Manual

　　Alinx Electronic Limited

Company Website: www.en.alinx.com

Service Hotline: +86 21 67676997

Technical Support : technical@alinx.com

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Document Information

Item	Content
Document Name	Product Manual
Product Model	AXW23
Document Version	V1.0
Prepared by	Alinx Electronic Limited
Release Date	2026.9.29

Document Revision History

Version	Date	Section	Revision Summary
V1.0	2026.9.29	All	Initial Release

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Part 1：Introduction

The AXW23 utilizes Xilinx's Zynq™ UltraScale+™ RFSoc Gen3 series ZU47DR FPGA main chip and XCVU13P - FHGB2104 (hereinafter referred to as XCVU13P) . The 47DR supports 8-channel 14-bit RF-ADC with a maximum sampling rate of 5 GSPS and 8-channel 14-bit RF-DAC with a maximum sampling rate of 9.85 GSPS . This reduces the complexity of the RF signal processing chain, maximizes input/output channel density without sacrificing bandwidth, utilizes heterogeneous processing capabilities, and boasts lower power consumption (eliminating ADC/DAC components and eliminating FPGA-to-analog interface power consumption). Zynq UltraScale+ devices provide an ARM Cortex-A53 processing subsystem, UltraScale+ programmable logic, and the highest signal processing bandwidth, enabling a comprehensive RF signal chain to meet the needs of wireless, cable TV access, test and measurement, early warning/radar, and other high-performance RF applications. The XCVU13P chip is also suitable for boards with large-scale data processing capabilities. The chip's powerful data processing capabilities enable its application in scenarios such as integrated radar, communication infrastructure, high-performance computing and artificial intelligence inference acceleration, and network data center accelerators. The main chip, XCVU13P, uses a 16nm FinFET+ process, ASIC-class architecture, and multiprocessor-on-a-chip (MPSoC) technology, containing 1728K configurable logic blocks, 3780K system logic units , 94.5Mbit of embedded memory, 76 high-speed GTY, and a maximum speed support of 32.75Gb/s .

The AXW23 features a rich array of peripheral interfaces, including one SD card interface, two 100 Gbps QSFP interfaces, two Gigabit Ethernet interfaces, one JTAG/UART interface, one FMC interface, a VPX interface, eight ADC interfaces, and eight DAC interfaces .

1.1 Product Overview

The AXW23 incorporates an AMD RFSoC and XCVU13P in a highly versatile design , making it suitable for various scenarios. The AXW23 receives 12V power via J23. On the RFSoC side, it utilizes five Micron MT40A1G16RC -062E IT:B DDR4 chips , with four DDR4 chips mounted on the PS side forming a 64-bit data bus and one DDR4 chip mounted on the PL side forming a 16- bit data bus. Each chip has a 2GB DDR4 capacity . A 32GB eMMC module is also included. Additionally, two 2Gbit NOR flash memory modules are integrated for boot memory configuration and system files. On the VU13P side, there are two 64-bit DDR4 SODIMM memory slots , and one 1Gbit NOR flash memory module is also integrated for boot memory configuration and system files . The board also features FMC and VPX interfaces , providing abundant peripheral resources and expandable high-speed interfaces.

1.2 Application Scenarios

　　Communication application scenarios

• 5G and LTE wireless technologies: With Zynq RFSoC, wireless infrastructure manufacturers can achieve significant reductions in footprint and power consumption, which is crucial for the future development of communications.

• Satellite communications: Designers can build high-speed, multi-functional instruments for signal generation and analysis by utilizing direct RF sampling, highly flexible, reconfigurable logic, and software programmability in the Zynq UltraScale+ RFSoC.

　　Radar application scenarios

• Radar signal processing and data link: Equipped with an 8-channel ADC and an 8-channel DAC, it can meet greater application requirements and achieve low-latency transmission and reception in early warning scenarios, thus obtaining the best response time.

　　Test and Measurement Application Scenarios

• Designers can leverage RF sampling, highly flexible and reconfigurable logic, and software programmability to build high-speed, multi-functional instruments for signal generation and analysis.

1.3 Product Features

1.4 Appearance​​

Figure 1.4.1 shows the appearance of the AXW23 . Currently, the product is delivered as a board. Our company also provides accessory delivery services. If you need other accessories to be delivered together, please contact our sales department in advance.

Figure 1.4.1- AXW23 Appearance Images TOP

Part 2：Board Hardware Introduction

2.1 Board Block Diagram

The core hardware block diagram of AXW23 is shown in Figure 2.1.1 :

Figure 2.1.1- AXW23 Hardware Block Diagram

2.2 Key Parameters

The main chips of AXW23 are XCZU47DR and VU13P . The key parameters of the board are shown in Table 2.2.1 below :

main chip	- XCZU47DR- XCVU13P_FHGB2104
size	- 90mm * 80.5mm
Expand memory	- PS DDR4 64-bit, 8GB- PL DDR4 16-bit, 2GB- DDR4 SODIMM memory slots *2 (VU13P)
storage	- RFSOC: Nor Flash 2Gb *2- VU13P: Nor Flash 1Gb *1
eMMC	- PS eMMC 32 GB
interface	- VPXRFSOC: - SD CARD- RGMII*2- ADC*8- DAC*8VU13P: - QSFP*2- FMC connectors
indicator lights	RFSOC: - INIT_B and DONE are two working status indicator lights.- PS_ERR_OUT and PS_ERR_STATUS are two working status indicator lights.VU13P: - DONE LED and INIT LED are two working status indicator lights.
Power supply for the board	12V power (via connector J23)
Power consumption	60W (based on actual measured value, depending on the application)
Ambient temperature requirements	Operating temperature: -40℃ to 70℃

Table 2.2.1- AXW23 Key Parameters

2.3 Functions and Locations of the Board

The functions and locations of some parts of this board are shown in the figure below , and the function description of each location is shown in Table 2.3.1. The functions of each position on the AXW23 are shown below:

Figure 2.3.1 - Identification diagram of AXW23 core functional blocks

serial number	Function
1	Main chip, XCZU47DR, reference number U1.
2	Main chip, VU13P , tag number U53 .
3	PS DDR4 extended memory , 64-bit bus width, total capacity 8 GB.
4	PL DDR4 extended memory , 16-bit bus width, 2GB total capacity.
5	VU13P DDR4 SODIMM1 memory slot (U30).
6	VU13P DDR4 SODIMM2 (U31) memory slot .
7	LMK04828.
8	100MHz crystal oscillator, LMK04828 OSCIN input clock.
9	47DR_QSPI Flash, 2Gbit capacity * 2 , stores code and data, U10 and U11.
10	VU13P_QSPI Flash, 1 Gbit capacity *1, stores code and data U54 .
11	47DR operating status indicator, PS_ERR_OUT.
12	47DR operating status indicator, PS_ERR_STATUS.
13	47DR working status indicator, PS_INIT_B.
14	47DR working status indicator, PS_DONE.
15	QSFP*2.
16	SD CARD.
17	12V power supply is on and functioning normally.
18	EMMC.
19	ADC.
20	DAC.
21	IN/OUT_TRIG, J5 .
22	47 DR_Ethernet RGMII-1.
23	10 0 M clock, LMK04828 OSCOUT input clock.
24	300MHz clock speed, used as the extended DDR4 operating clock reference.
25	47 DR USB_JTAG.
26	FMC.
27	VPX.
28	47DR_JTAG interface.
29	VU13P JTAG.
30	12V fan connector.
31	VU13P users can customize the LEDs.
32	Users can customize the I/O.
33	47DR users can customize the LEDs.
34	12V power interface.
35	47DR mode switch SW1.

Table 2.3.1- Functional description of each position of AXW23

2.4 Startup Mode​

The XCZU47DR has four boot modes: JTAG mode, QSPI mode, SD card mode, and EMMC mode. The boot mode of the XCZU47DR can be configured via a DIP switch (which needs to be reserved on the baseboard).

The main chip of this board, XCZU47DR (reference number U1), is an RFSOC FPGA. The boot mode is determined by the high/low states of four pins: PS_MODE0 , PS_MODE1, PS_MODE2, and PS_MODE3. The board uses a four-position switch (reserved on the baseboard) to select the device configuration mode. Table 2.4.1 illustrates the configuration modes corresponding to each state of the XCZU47DR.

BOOT mode	Mode pin [3:0]	SW[4:1]
JTAG	0000	ON, ON, ON, ON
QSPI	0010	ON, ON, OFF, ON
eMMC	0110	ON, OFF, OFF, ON
SD	0101	ON, OFF, ON, OFF

Table 2.4.1 - Correspondence of Mode Pins on the PS Terminal of XCZU47DR

The main chip of this board, XCVU13P (reference number U53), is a pure logic FPGA. The boot mode is determined by the high/low states of three pins: M0, M1, and M2. The board defaults to QSPI Flash boot mode. The pin states for the boot mode are shown in the table below for XCVU13P QSPI Flash boot mode:

FPGA pin numbers	FPGA pin names	Level state
U53.V12	M0	high
U53.U12	M1	Low
U53.R12	M2	Low

Table 2.4.2 - XCVU13P QSPI Flash Boot Mode Configuration Table

Note: The main chip of the board is an FPGA with pure logic units. When mounting JTAG, there is no need to modify the Mode[2:0] state of boot mode. The XCVU13P can be recognized by directly connecting to VIVADO.

2.5 DDR4 Memory​

As shown in the AXW23 hardware block diagram, the main chip XCZU47DR of this board is configured with two sets of DDR4 extended memory. Four DDR4 chips are installed on the PS side to form a 64-bit data bus width, and one DDR4 chip is installed on the PL side to form a 16 -bit data bus width. It consists of five Micron MT40A1G16RC-062E IT:B chips. The board's VU13P uses two DDR4 SO-DIMMs, both using a 300MHz differential crystal oscillator as the reference clock. The specific DDR4 configuration on the PS and PL sides is shown in the table below :

Location	Position	Chip Model	capacity	factory
PS	U 33 , U 34 , U 35 , U 36	MT40A1G16RC-062E IT:B	1G x16bit	Micron
PL	U 37	MT40A1G16RC-062E IT:B	1G x16bit	Micron

Table 2.5.1 - DDR4 Configuration

The hardware connection method for DDR4 on the PS side is shown in the following figure:

Figure 2.5.1 - Schematic diagram of DDR4 connection at the PS end

The hardware connection method for DDR4 on the PL side is as follows:

Figure 2.5.2- DDR4 connection diagram at PL end

Note: 1. Although memory chips support a transfer rate of up to 3200MT/s , FPGA chips support a maximum transfer rate of 2400 Mb/s . Please refer to the chip datasheet for details.

2. This section shows the highest performance parameters for the memory and main chip (which also means the highest power consumption). Users can adjust these parameters according to their usage scenarios to balance power consumption and performance.

The hardware connection method for the DDR4 memory slots of the VU13P is as follows:

Figure 2.5.3 - Schematic diagram of DDR4 SODIMM memory slot connection at the XCVU13P end

2.6 QSPI FLASH​

Features two MT25QU02GCBB8E12-0SIT serial Nor Flash memory chips on the XCZU47DR PS side and one MT25QU01GBBB8E12-0SIT chip on the XCVU13P side. Both can be used to store executable code and data, such as bootloaders, operating systems, and bitstreams. The two QSPI chips on the 47DR side are connected in parallel.

To achieve higher performance, two Quad-SPI devices are connected in parallel on the XCZU47DR side , providing a total of 8 bits of data bus for booting and configuration. The XCZU47DR is connected to two QSPI Nor Flash chips , as shown below:

Figure 2.6.1 - Schematic diagram of interconnection between two QSPI Nor Flash chips and XCZU47DR

The interconnect pin definitions for the two QSPI Nor Flash chips are as follows :

FPGA pin numbers	FPGA pin names	signal name	pin number	QSPI pin names
U1.MIO12_B15	PS_MIO12_B15	MIO12_QSPI_UPR_CLK	U11.B2	C
U1.MIO10_C15	PS_MIO10_C15	MIO10_QSPI_UPR_DQ2	U11.C4	DQ2_W_B
U1.MIO9_F15	PS_MIO9_F15	MIO9_QSPI_UPR_DQ1	U11.D2	DQ1
U1.MIO8_E15	PS_MIO8_E15	MIO8_QSPI_UPR_DQ0	U11.D3	DQ0
U1. MIO11_G16	PS_MIO11_G16	MIO11_QSPI_UPR_DQ3	U11.D4	DQ3_RST_HLD_B
U1.MIO7_K17	PS_MIO7_K17	MIO7_QSPI_UPR_CS_B	U11.C2	S_B
U1.MIO5_H18	PS_MIO5_H18	MIO5_QSPI_LWR_CS_B	U10.C2	S_B
U1.MIO4_G15	PS_MIO4_G15	MIO4_QSPI_LWR_DQ0	U10.D3	DQ0
U1.MIO3_K16	PS_MIO3_K16	MIO3_QSPI_LWR_DQ3	U10.D4	DQ3_RST_HLD_B
U1.MIO2_J16	PS_MIO2_J16	MIO2_QSPI_LWR_DQ2	U10.C4	DQ2_W_B
U1.MIO1_J18	PS_MIO1_J18	MIO1_QSPI_LWR_DQ1	U10.D2	DQ1
U1.MIO0_J17	PS_MIO0_J17	MIO0_QSPI_LWR_CLK	U10.B2	C

Table 2.6.1 - Interconnection Pin Definitions between Two QSPI Nor Flash Chips and XCZU47DR

Figure 2.6.2 - Schematic diagram of interconnection between a QSPI Nor Flash chip and a VU13P chip.

The pin definitions for 1 QSPI Nor Flash interconnect are as follows

FPGA pin numbers	FPGA pin names	signal name	pin number	QSPI pin names
U 53.AG13	CCLK_0_AG13	FPGA_CCLK	U 54 .B2	C
U 53. AL12	D02_0_AL12	SPI0_WP#	U 54 .C4	DQ2_W_B
U 53.AJ12	D01_DIN_0_AJ12	SPI0_DQ1	U 54 .D2	DQ1
U 53.AK12	D00_MOSI_0_AK12	SPI0_DQ0	U 54 .D3	DQ0
U 53.AH12	D03_0_AH12	SPI0_HOLD_B	U 54 .D4	DQ3_RST_HLD_B
U 53.AG12	RDWR_FCS_B_0_AG12	SPI0_CS_B	U 54 .C2	S_B

Table 2.6.2 - Pin Definitions for Interconnection between a QSPI Nor Flash Chip and the VU13P

2.7 eMMC​​

The AXW23 provides eMMC storage. It connects to the PS pin of the main chip 47DR for direct data exchange with the main chip. A schematic diagram of the overall eMMC connection is shown below:

Figure 2.7.1- eMMC Overall Connection Diagram

eMMC Pin Assignment Table:

Signal name	pin name	pin number
eMMC_DS	PS_MIO25_B17	B17
MIO23_eMMC_RST	PS_MIO23_D17	D17
MIO22_eMMC_CLK	PS_MIO22_E17	E17
MIO21_eMMC_CMD	PS_MIO21_F17	F17
MIO20_eMMC_DAT7	PS_MIO20_B16	B16
MIO20_eMMC_DAT6	PS_MIO19_C16	C16
MIO18_eMMC_DAT5	PS_MIO18_F18	F18
MIO17_eMMC_DAT4	PS_MIO17_E16	E16
MIO16_eMMC_DAT3	PS_MIO16_G17	G17
MIO15_eMMC_DAT2	PS_MIO15_D16	D16
MIO14_eMMC_DAT1	PS_MIO14_A15	A15
MIO13_eMMC_DAT0	PS_MIO13_G18	G18

Table 2.7.1 - eMMC Pin Assignment

2.8 EEPROM​​

The core board has an onboard EEPROM, model M24C08-RDW6TP, with a capacity of 8Kb, which is connected to the PL terminal for communication via the IIC bus. The EEPROM pin assignment is shown in the table below :

Signal name	pin name	pin number	Remark
IIC_EEPROM_SCL	IO_L9N_AD3N_89_H9	H9	I2C data signal
IIC_EEPROM_SDA	IO_L9P_AD3P_89_H10	H10	I2C clock signal

Table 2.8.1 - EEPROM Pin Definitions

2.9 Micro SD Card Slot

The AXW23 includes a Micro SD card interface derived from the RFSOC , providing user access to SD card storage for storing the boot program, Linux operating system kernel, file system, and other user data files. The SD card I/O signals are connected to the MIO signals of the PS BANK501 . A schematic diagram of the PS and SD card connector connection is shown below:

Figure 2.9.1- SD card connection diagram

SD card pin assignment :

Signal name	pin name	pin number	Remark
SDIO_CLK	PS_MIO51_B21	B21	SD clock signal
SDIO_CMD	PS_MIO50_A22	A22	SD command signals
SDIO_DAT0	PS_MIO46_A20	A20	SD data Bit0
SDIO_DAT1	PS_MIO47_D21	D21	SD data Bit1
SDIO_DAT2	PS_MIO48_C21	C21	SD data Bit2
SDIO_DAT3	PS_MIO49_E21	E21	SD data Bit3
SDIO_DETECT	PS_MIO45_B20	B20	SD card detection signal

Table 2.9.1 - SD Card Pin Assignment

2.10 JTAG & UART

The AXW23 has a reserved JTAG & UART interface for downloading and debugging FPGA programs or burning programs to FLASH. We used FTDI's 5th generation USB device chip, the FT4232HL-REEL , which is a USB 2.0 high-speed to UART/FIFO chip with two multi-protocol synchronous serial engines allowing JTAG. It has the capability to be configured with various industry-standard serial or parallel interfaces. The JTAG & UART connection diagram is shown below :

Figure 2.10.1- RFSOC side JTAG & UART connector connection diagram

Signal name	pin name	pin number	Remark
UART0_RXD_MIO39_TXD	PS_MIO39_D19	D19	PS UART data output
UART0_TXD_MIO38_RXD	PS_MIO38_B18	B18	PS UART data input

Table 2.10.1- RFSOC Side JTAG & UART Pin Assignment

2.11 Gigabit Ethernet Interface

The AXW23 has two Gigabit Ethernet ports connected to the RJ45 and VPX-P1 ports respectively . The Ethernet chip used is the MARVELL 88E1512-A0-NNP2I000 chip to provide network communication services. The Ethernet PHY chip on the PS side is connected to the MIO port of the ZYNQ's PS-side BANK501 . The 88E1512-A0-NNP2I000 chip supports 10/100/1000 Mbps network transmission rates and communicates with the ZYNQ system's MAC layer via the RGMII interface. A schematic diagram of the Gigabit Ethernet PHY chip connection is shown below :

Figure 2.11.1 - Schematic diagram of Ethernet connection

Signal name	pin name	pin number	PHY chip
			pin number	pin name
MIO64_ENET_TX_CLK	PS_MIO64_ D24	D24	53	TX_CLK
ENET_TX_D0	PS_MIO65_ C24	C24	50	TXD0
ENET_TX_D1	PS_MIO66_ F24	F24	51	TXD 1
ENET_TX_D2	PS_MIO67_ F25	F25	54	TXD 2
ENET_TX_D3	PS_MIO68_ E25	E25	55	TXD 3
ENET_TX_CTRL	PS_MIO69_ E24	E24	56	TX_CTRL
ENET_RX_CLK	PS_MIO70_ B25	B25	46	RX_CLK​
ENET_RX_D0	PS_MIO71_ A24	A24	44	RXD0
ENET_RX_D1	PS_MIO72_ C25	C25	45	RXD 1
ENET_RX_D2	PS_MIO73_A 25	A25	47	RXD 2
ENET_RX_D3	PS_MIO74_ C26	C26	48	RXD 3
ENET_RX_CTRL	PS_MIO75_ B26	C26	43	RX_CTRL
ENET_MDC	PS_MIO76_ E26	E26	7	MD C
ENET_MDIO	PS_MIO77_ D26	D26	8	MDIO
MIO42_ETH_RESET#	PS_MIO4 2_E20	E20	16	RESET_B
PS_POR_B	PS_POR_B_N24	N24
MIO52_ENET_TX_CLK	PS_MIO52_G22	G22	53	TX_CLK
MIO53_ENET_TX_D0	PS_MIO53_F22	F22	50	TXD0
MIO54_ENET_TX_D1	PS_MIO54_H23	H23	51	TXD 1
MIO55_ENET_TX_D2	PS_MIO55_D22	D22	54	TXD 2
MIO56_ENET_TX_D3	PS_MIO56_G23	G23	55	TXD 3
MIO57_ENET_TX_CTRL	PS_MIO52_G22	G22	56	TX_CTRL
MIO58_ENET_RX_CLK	PS_MIO58_B22	B22	46	RX_CLK​
MIO59_ENET_RX_D0	PS_MIO59_D23	D23	44	RXD0
MIO60_ENET_RX_D1	PS_MIO60_A23	A23	45	RXD 1
MIO61_ENET_RX_D2	PS_MIO61_E22	E22	47	RXD 2
MIO62_ENET_RX_D3	PS_MIO62_B23	B23	48	RXD 3
MIO63_ENET_RX_CTRL	PS_MIO63_C23	C23	43	RX_CTRL
PL_ENET_MDC	IO_L3P_AD13P_88_J14	J14	7	MD C
PL_ENET_MDIO	IO_L3N_AD13N_88_J13	J13	8	MDIO
MIO43_ETH_RESET#	P S_MIO43_A19	A19	16	RESET_B
PS_POR_B	PS_POR_B_N24	N24

Table 2.11.1- PHY to XCZU47DR pin assignment

2.12 Fiber Optic Interface

The AXW23 has two QSFP interfaces connected to the VU13P . The two fiber optic interfaces are connected to BANK127 and BANK130 of the VU13P , respectively. The GT BANK's reference clock can be provided by the differential crystal oscillator on the AXW23 at 156.25MHz . A schematic diagram of the fiber optic interface connections is shown below:

Figure 2.12.1 - Schematic diagram of fiber optic design

Signal name	ZYNQ pin name	ZYNQ pin number
QSFP1_TX1_P	MGTYTXP0_127_AJ40	AJ40
QSFP1_TX1_N	MGTYTXN0_127_AJ41	AJ41
QSFP1_RX1_P	MGTYRXP0_127_AJ45	AJ45
QSFP1_RX1_N	MGTYRXN0_127_AJ46	AJ46
QSFP1_TX2_P	MGTYTXP1_127_AH38	AH38
QSFP1_TX2_N	MGTYTXN1_127_AH39	AH39
QSFP1_RX2_P	MGTYTXP3_127_AH43	AH43
QSFP1_RX2_N	MGTYTXN3_127_AH44	AH44
QSFP1_TX3_P	MGTYTXP2_127_AG40	AG40
QSFP1_TX3_N	MGTYTXN2_127_AG41	AG41
QSFP1_RX3_P	MGTYRXP2_127_AG45	AG45
QSFP1_RX3_N	MGTYRXN2_127_AG46	AG46
QSFP1_TX4_P	MGTYTXP3_127_AF38	AF38
QSFP1_TX4_N	MGTYTXN3_127_AF39	AF39
QSFP1_RX4_P	MGTYRXP3_127_AF43	AF43
QSFP1_RX4_N	MGTYRXN3_127_AF44	AF44
QSFP2_TX1_P	MGTYTXP0_130_U40	U40
QSFP2_TX1_N	MGTYTXN0_130_U41	U41
QSFP2_RX1_P	MGTYRXP0_130_U45	U45
QSFP2_RX1_N	MGTYRXN0_130_U46	U46
QSFP2_TX2_P	MGTYTXP1_130_T38	T38
QSFP2_TX2_N	MGTYTXN1_130_T39	T39
QSFP2_RX2_P	MGTYTXP3_130_T43	T43
QSFP2_RX2_N	MGTYTXN3_130_T44	T44
QSFP2_TX3_P	MGTYTXP2_130_R40	R40
QSFP2_TX3_N	MGTYTXN2_130_R41	R41
QSFP2_RX3_P	MGTYRXP2_130_R45	R45
QSFP2_RX3_N	MGTYRXN2_130_R46	R46
QSFP2_TX4_P	MGTYTXP3_130_P38	P38
QSFP2_TX4_N	MGTYTXN3_130_P39	P39
QSFP2_RX4_P	MGTYRXP3_130_P43	P43
QSFP2_RX4_N	MGTYRXN3_130_P44	P44

Table 2.12.1- Q SFP Interface Pin Assignment

Signal name	ZYNQ pin name	pin number	Remark
GT130_QSFP2_CLK0P	MGTREFCLK0P_130_W36	W36	The OUT2 output of CDCLVD1204RGTR has a default configured 156.25 MHz crystal oscillator.
GT130_QSFP2_CLK0N	MGTREFCLK0N_130_W37	W37	The OUT2 output of CDCLVD1204RGTR has a default configured 156.25 MHz crystal oscillator.
GT127_QSFP1_CLK0P	MGTREFCLK0P_127_AL36	AL36	The OUT1 output of CDCLVD1204RGTR uses a 156.25 MHz crystal oscillator by default, with the option to output from the Si5341.
GT127_QSFP1_CLK0N	MGTREFCLK0N_127_AL37	AL37	The OUT1 output of CDCLVD1204RGTR uses a 156.25 MHz crystal oscillator by default, with the option to output from the Si5341.

Table 2.12.2 - Reference Clock Allocation for BANK127 and BANK130

Low-speed control I/O processing:

QSFP Low-speed I/O signal name	Remark
MODSELL	pull down GND
ResetL	3.3V pull-up
MODPRSL	3.3V pull-up
SDA	3.3V pull-up
SCL	3.3V pull-up
intL	3.3V pull-up
LPMode	pull down GND

Table 2.12.3 - Fiber Optic Low-Speed I/O Signal Processing Methods

2.13 RF Interface

The AXW23 uses the Zynq™ UltraScale+™ RFSoC Gen3 series, the industry's only single-chip adaptive radio platform. The chip integrates a 14-bit RF-ADC with a maximum sampling rate of 5GSPS, and the VCM signal is also brought out to the connector for easy adjustment of the common-mode voltage.

Figure 2.13.1 - RF-ADC Interface Diagram

AXW23 uses the Zynq™ UltraScale+™ RFSoC Gen3 series, the industry's only single-chip adaptive radio platform, which integrates a 14-bit RF-DAC with a maximum sampling rate of 9.85 GSPS.

Figure 2.13.2- RF-DAC Interface Diagram

2.14 FMC Interface

This board provides an external connection interface using FMC. Other functions outside the board can be implemented through external daughter cards.The principle block diagram for this part is shown in the figure below:

Figure 2.14.1- FMC Interface Diagram

Signal name	FMC PIN	ZYNQ pin number	ZYNQ pin name
FMCP_HSPC_DP1_M2C_P	A2	BA45	MGTYRXP1_120_BA45
FMCP_HSPC_DP1_M2C_N	A3	BA4 6	MGTYRXN1_120_BA46
FMCP_HSPC_DP2_M2C_P	A6	AW45	MGTYRXP2_120_AW45
FMCP_HSPC_DP2_M2C_N	A7	AW46	MGTYRXN2_120_AW46
FMCP_HSPC_DP3_M2C_P	A10	AV43	MGTYRXP3_120_AV43
FMCP_HSPC_DP3_M2C_N	A11	AV44	MGTYRXN3_120_AV44
FMCP_HSPC_DP4_M2C_P	A14	AU45	MGTYRXP0_121_AU45
FMCP_HSPC_DP4_M2C_N	A15	AU46	MGTYRXN0_121_AU46
FMCP_HSPC_DP5_M2C_P	A18	AT43	MGTYRXP1_121_AT43
FMCP_HSPC_DP5_M2C_N	A19	AT44	MGTYRXN1_121_AT44
FMCP_HSPC_DP1_C2M_P	A22	BD42	MGTYTXP1_120_BD42
FMCP_HSPC_DP1_C2M_N	A23	BD43	MGTYTXN1_120_BD43
FMCP_HSPC_DP2_C2M_P	A26	BB42	MGTYTXP2_120_BB42
FMCP_HSPC_DP2_C2M_N	A27	BB43	MGTYTXN2_120_BB43
FMCP_HSPC_DP3_C2M_P	A30	AW40	MGTYTXP3_120_AW40
FMCP_HSPC_DP3_C2M_N	A31	AW41	MGTYTXN3_120_AW41
FMCP_HSPC_DP4_C2M_P	A34	AU40	MGTYTXP0_121_AU40
FMCP_HSPC_DP4_C2M_N	A35	AU41	MGTYTXN0_121_AU41
FMCP_HSPC_DP5_C2M_P	A38	AT38	MGTYTXP1_121_AT38
FMCP_HSPC_DP5_C2M_N	A39	AT39	MGTYTXN1_121_AT39
FMCP_HSPC_DP9_M2C_P	B4	AM43	MGTYRXP1_122_AM43
FMCP_HSPC_DP9_M2C_N	B5	AM44	MGTYRXN1_122_AM44
FMCP_HSPC_DP8_M2C_P	B8	AN45	MGTYRXP0_122_AN45
FMCP_HSPC_DP8_M2C_N	B9	AN46	MGTYRXN0_122_AN46
FMCP_HSPC_DP7_M2C_P	B12	AP43	MGTYRXP3_121_AP43
FMCP_HSPC_DP7_M2C_N	B13	AP44	MGTYRXN3_121_AP44
FMCP_HSPC_DP6_M2C_P	B16	AR45	MGTYRXP2_121_AR45
FMCP_HSPC_DP6_M2C_N	B17	AR46	MGTYRXN2_121_AR46
FMCP_HSPC_GBTCLK1_M2C_P	B20	AV38	MGTREFCLK0P_121_AV38
FMCP_HSPC_GBTCLK1_M2C_N	B21	AV39	MGTREFCLK0N_121_AV39
FMCP_HSPC_DP9_C2M_P	B24	AM38	MGTYTXP1_122_AM38
FMCP_HSPC_DP9_C2M_N	B25	AM39	MGTYTXN1_122_AM39
FMCP_HSPC_DP8_C2M_P	B28	AN40	MGTYTXP0_122_AN40
FMCP_HSPC_DP8_C2M_N	B29	AN41	MGTYTXN0_122_AN41
FMCP_HSPC_DP7_C2M_P	B32	AP38	MGTYTXP3_121_AP38
FMCP_HSPC_DP7_C2M_N	B33	AP39	MGTYTXN3_121_AP39
FMCP_HSPC_DP6_C2M_P	B36	AR40	MGTYTXP2_121_AR40
FMCP_HSPC_DP6_C2M_N	B37	AR41	MGTYTXN2_121_AR41
FMCP_HSPC_DP0_C2M_P	C2	BF42	MGTYTXP0_120_BF42
FMCP_HSPC_DP0_C2M_N	C3	BF43	MGTYTXN0_120_BF43
FMCP_HSPC_DP0_M2C_P	C6	BC45	MGTYRXP0_120_BC45
FMCP_HSPC_DP0_M2C_N	C7	BC46	MGTYRXN0_120_BC46
FMCP_HSPC_LA06_P	C10	AN23	IO_L20P_T3L_N2_AD1P_64_AN23
FMCP_HSPC_LA06_N	C11	AP23	IO_L20N_T3L_N3_AD1N_64_AP23
FMCP_HSPC_LA10_P	C14	AR17	IO_L16P_T2U_N6_QBC_AD3P_66_AR17
FMCP_HSPC_LA10_N	C15	AT17	IO_L16N_T2U_N7_QBC_AD3N_66_AT17
FMCP_HSPC_LA14_P	C18	BB17	IO_L5P_T0U_N8_AD14P_66_BB17
FMCP_HSPC_LA14_N	C19	BC17	IO_L5N_T0U_N9_AD14N_66_BC17
FMCP_HSPC_LA18_CC_P	C22	AV19	IO_L12P_T1U_N10_GC_66_AV19
FMCP_HSPC_LA18_CC_N	C23	AW19	IO_L12N_T1U_N11_GC_66_AW19
FMCP_HSPC_LA27_P	C26	AL22	IO_L23P_T3U_N8_64_AL22
FMCP_HSPC_LA27_N	C27	AM22	IO_L23N_T3U_N9_64_AM22
FMCP_HSPC_IIC_SCL	C30	F25	I O_T2U_N12_72_F25
FMCP_HSPC_IIC_SDA	C31	H22	I O_T1U_N12_72_H22
FMCP_HSPC_GBTCLK0_M2C_P	D4	BA40	MGTREFCLK0P_120_BA40
FMCP_HSPC_GBTCLK0_M2C_N	D5	BA41	MGTREFCLK0N_120_BA41
FMCP_HSPC_LA01_CC_P	D8	AT19	IO_L13P_T2L_N0_GC_QBC_66_AT19
FMCP_HSPC_LA01_CC_N	D9	AU19	IO_L13N_T2L_N1_GC_QBC_66_AU19
FMCP_HSPC_LA05_P	D11	AN22	IO_L19P_T3L_N0_DBC_AD9P_64_AN22
FMCP_HSPC_LA05_N	D12	AN21	IO_L19N_T3L_N1_DBC_AD9N_64_AN21
FMCP_HSPC_LA09_P	D14	AP18	IO_L17P_T2U_N8_AD10P_66_AP18
FMCP_HSPC_LA09_N	D15	AR18	IO_L17N_T2U_N9_AD10N_66_AR18
FMCP_HSPC_LA13_P	D17	AY17	IO_L7P_T1L_N0_QBC_AD13P_66_AY17
FMCP_HSPC_LA13_N	D18	BA17	IO_L7N_T1L_N1_QBC_AD13N_66_BA17
FMCP_HSPC_LA17_CC_P	D20	AV18	IO_L11P_T1U_N8_GC_66_AV18
FMCP_HSPC_LA17_CC_N	D21	AW18	IO_L11N_T1U_N9_GC_66_AW18
FMCP_HSPC_LA23_P	D23	AL21	IO_L22P_T3U_N6_DBC_AD0P_64_AL24
FMCP_HSPC_LA23_N	D24	AM24	IO_L22N_T3U_N7_DBC_AD0N_64_AM24
FMCP_HSPC_LA26_P	D26	AL21	IO_L24P_T3U_N10_64_AL21
FMCP_HSPC_LA26_N	D27	AM21	IO_L24N_T3U_N11_64_AM21
FMCP_HSPC_CLK1_M2C_P	G2	AY23	IO_L12P_T1U_N10_GC_64_AY23
FMCP_HSPC_CLK1_M2C_N	G3	BA23	IO_L12N_T1U_N11_GC_64_BA23
FMCP_HSPC_LA00_CC_P	G6	AT20	IO_L14P_T2L_N2_GC_66_AT20
FMCP_HSPC_LA00_CC_N	G7	AU20	IO_L14N_T2L_N3_GC_66_AU20
FMCP_HSPC_LA03_P	G9	AN24	IO_L21P_T3L_N4_AD8P_64_AN24
FMCP_HSPC_LA03_N	G10	AP24	IO_L21N_T3L_N5_AD8N_64_AP24
FMCP_HSPC_LA08_P	G12	BB19	IO_L6P_T0U_N10_AD6P_66_BB1 9
FMCP_HSPC_LA08_N	G13	BC18	IO_L6N_T0U_N11_AD6N_66_BC18
FMCP_HSPC_LA12_P	G15	AT18	IO_L15P_T2L_N4_AD11P_66_AT18
FMCP_HSPC_LA12_N	G16	AU17	IO_L15N_T2L_N5_AD11N_66_AU17
FMCP_HSPC_LA16_P	G18	AY18	IO_L8P_T1L_N2_AD5P_66_AY18
FMCP_HSPC_LA16_N	G19	BA18	IO_L8N_T1L_N3_AD5N_66_BA18
FMCP_HSPC_LA20_P	G21	BE17	IO_L1P_T0L_N0_DBC_66_BE17
FMCP_HSPC_LA20_N	G22	BF17	IO_L1N_T0L_N1_DBC_66_BF17
FMCP_HSPC_LA22_P	G24	AV21	IO_L10P_T1U_N6_QBC_AD4P_66_AV21
FMCP_HSPC_LA22_N	G25	AW21	IO_L10N_T1U_N7_QBC_AD4N_66_AW21
FMCP_HSPC_LA25_P	G27	AR22	IO_L16P_T2U_N6_QBC_AD3P_64_AR22
FMCP_HSPC_LA25_N	G28	AT22	IO_L16N_T2U_N7_QBC_AD3N_64_AT22
FMCP_HSPC_LA29_P	G30	AL20	IO_L24P_T3U_N10_66_AL20
FMCP_HSPC_LA29_N	G31	AM20	IO_L24N_T3U_N11_66_AM20
FMCP_HSPC_LA31_P	G33	AN18	IO_L19P_T3L_N0_DBC_AD9P_66_AN18
FMCP_HSPC_LA31_N	G34	AN17	IO_L19N_T3L_N1_DBC_AD9N_66_AN17
FMCP_HSPC_LA33_P	G36	AM16	IO_L21P_T3L_N4_AD8P_66_AM16
FMCP_HSPC_LA33_N	G37	AN16	IO_L21N_T3L_N5_AD8N_66_AN16

Table 2.14.1 - FMC Partial Interface Pin Assignment Table

2.15 VPX

The AXW23 board features a 6U VPX architecture, offering guarantees in performance, compatibility, and reliability. The VPX architecture typically utilizes high-speed serial switching technology and supports multiple protocols. It boasts high-speed performance, supporting high-speed serial interfaces for high-speed data transmission. This is crucial for applications requiring rapid processing of large amounts of data, such as radar and signal processing. It offers strong scalability; the modular design of the VPX architecture allows users to add or replace different functional modules within the system to adapt to diverse application needs. It also offers good compatibility, enabling interchangeability of modules from different manufacturers, reducing the complexity of system integration.

Figure 2.15.1 - VPX Interface Diagram

2.16 Interconnection

The AXW23 supports the GTY high-speed transceiver, enabling interconnection between the XCZU47DR and VU13P with a data rate up to 25.0Gb/s. LVDS interconnection between the XCZU47DR and VU13P is achieved using PL BANK IO . This facilitates secondary development by users for data transmission, minimizing design risk and offering flexibility.

Figure 2.16.1-47DR and VU13P interconnection diagram

2.17 Indicator lights

　　Main chip status indicator:

The main chip XCZU47DR (reference number U1) on this board has four status indicator lights . The function status indicated by each LED on the 47DR is shown in the table below :

LED number	Indicator light color	Function
DS1	red	FPGA initialization error
DS2	red	FPGA download error
DS3	red	PS_ERR_OUT indicator light
DS4	red	PS_ERR_STATUS indicator light

Table 2.17.1 - Function Description of Status Indicator Lights on Main Chip XCZU47DR

VU13P (reference number U 53 ) on this board has three status indicator lights . The function descriptions of the VU13P status indicator lights are shown in the table below :

LED number	Indicator light color	Function
DS1 3	green	FPGA Download
DS 14	red	FPGA initialization.
DS 15	red	FPGA initialization error.

Table 2.17.2 - Function Description of Main Chip VU13P Status Indicator Lights

　　Power indicator light for the entire board:

Introduced to the AXW23 via connector J23. When the input power is normal, the power indicator DS22 will be highlighted green. The DS22 indicator is located at position 17. A schematic diagram of the specific location of the DS22 power indicator is shown below :

Figure 2.17.1 - Schematic diagram of the location of power indicator DS22

2.18 Clock Configuration

The AXW23 uses dual oscillators for the 47DR, with the system clock using a 33.3333MHz active crystal oscillator by default. The crystal operates at 32.768kHz and drives the internal RTC circuitry. A schematic diagram of the clock circuit design is shown below:

The AXW23 uses the LMK04828 clock chip to distribute the clocks required by each module of the 47DR , and the main crystal oscillator is a 100MHz crystal oscillator. It supports GTY clock recovery, external reference clock input, and SYSREF input, and can realize the parallel connection of multiple modules to form a larger-scale coherent RF channel.

Figure 2.18.1 - Schematic diagram of the overall clock topology

2.19 Power Supply

The AXW23 uses a 12V DC power supply, which is provided through the connector backplane . The 12V system power supply is converted into different voltages by a buck regulator to drive the FPGA and other circuits on the board. The power supply for the board's ADC and DAC is provided by a linear low-voltage LDO, which has good power supply rejection (PSRR). The extended I/O BANK interface levels of the 47DR core module are as follows :

BANK	Level	Remark
BANK65	1.2V	Primarily used for DDR4, it interconnects the remaining I/O with the VU13P in the form of LVDS.
BANK6 6	1.2V	Primarily used for DDR4, it pulls the remaining I/O pins to the header and interconnects with the VU13P via LVDS.
BANK88	1.8V	HD_BANK supports 1.2~3.3V (HD I/O only) at ±5%
BANK89	3.3V	HD_BANK supports 1.2~3.3V (HD I/O only) at ±5%
BANK128	MGTY (1.2V)	GTY signal
BANK129	MGTY (1.2V)	GTY signal
BANK501	1.8V	SD CARD
BANK502	1.8V	network port
BANK503	1.8V fixed	Configure pin outputs, mode selection, and system reset signal.
BANK505	PS_MGTR	PCIe, pull the signal to VPX-P1

Table 2.19.1-47DR IO BANK Interface Levels

The extended IO BANK interface levels of the VU13P core module are as follows :

BANK	Level	Remark
BANK 0	1.8 V​	Configure pin outputs, mode selection, QSPI
BANK 40 BANK41 BANK42	1.2V	Primarily used for DDR4, it pulls the remaining I/O pins to the connector.
BANK 46 BANK47 BANK48	1.2V	Primarily used for DDR4, it pulls the remaining I/O pins and LED1.
BANK 64 BANK65 BANK66	1.8 V	FMC, VPX
BANK67 BANK68	1.8 V	FMC, VPX
BANK70 BANK72	1.8 V	FMC, VPX
BANK71	1.2V	Interconnected with 47DR in LVDS format
BANK127 BANK130	MGTY (1.2V)	QSFP
BANK129	MGTY (1.2V)	GTY signal

Table 2.19.2 - VU13P IO BANK Interface Levels

Figure 2.19.1 - Overall power supply structure tree

2.20 Structural Dimensions Drawing

Figure 2.20.1- AXW23 front structure diagram

Appendix: List of Abbreviations

Abbreviation	Full English Name	Description
PS	Processor System	The processing subsystem in an SoC, typically including CPU cores, memory controllers, and peripheral interfaces for running software and operating systems.
PL	Programmable Logic	User-configurable FPGA logic resources used to implement custom digital circuits, interface controllers, and hardware acceleration functions.
SOC	System on Chip	An integrated circuit that combines processors, memory controllers, peripheral interfaces, and other system functions on a single chip.
DDR3	Double Data Rate 3 SDRAM	A third-generation synchronous dynamic memory technology that transfers data on both edges of the clock signal and is commonly used as system memory.
eMMC	Embedded Multi Media Card	An embedded non-volatile storage device that integrates NAND Flash memory and a storage controller in a single package.
QSPI	Quad Serial Peripheral Interface	A high-speed serial interface that uses four data lines and is commonly used to connect NOR Flash devices for boot or configuration storage.
GTP	Gigabit Transceiver	A high-speed serial transceiver integrated in an FPGA for transmitting and receiving data at multi-gigabit rates.
UART	Universal Asynchronous Receiver/Transmitter	An asynchronous serial communication interface that transmits and receives data through TX and RX signal lines.
HDMI	High-Definition Multimedia Interface	A digital multimedia interface used to transmit high-definition video and audio signals between source and display devices.
PCIe	Peripheral Component Interconnect Express	A high-speed serial expansion bus standard used for communication between processors and devices such as FPGAs, GPUs, and SSDs.
USB	Universal Serial Bus	A standard serial interface used for data communication, peripheral connection, and power delivery between electronic devices.
JTAG	Joint Test Action Group	A standardized interface used for device testing, boundary scan, FPGA programming, and processor or system debugging.
SFP	Small Form-factor Pluggable	A compact, hot-pluggable transceiver interface used for optical or electrical network communication.
MIO	Multiplexed I/O	Multiplexed processor I/O pins in an SoC that can be configured for functions such as UART, I2C, SPI, or GPIO.
GPHY	Gigabit Ethernet PHY	A Gigabit Ethernet physical-layer transceiver that converts digital Ethernet data into electrical signals for transmission over a physical network medium.
I2C	Inter-Integrated Circuit	A two-wire serial communication bus using SDA and SCL lines, commonly used to connect sensors, EEPROMs, and peripheral devices.
RGMII	Reduced Gigabit Media Independent Interface	A reduced-pin-count interface between an Ethernet MAC and PHY that supports 10, 100, and 1000 Mbps Ethernet communication.
RMII	Reduced Media Independent Interface	A reduced-pin-count interface between an Ethernet MAC and PHY, mainly used for 10 and 100 Mbps Ethernet communication.
LED	Light Emitting Diode	A semiconductor device that emits light when electrically driven and is commonly used for power, status, and fault indication.
LVDS	Low-Voltage Differential Signaling	A high-speed differential signaling standard that provides low power consumption, low noise, and strong resistance to electromagnetic interference.

Contact information

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