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ACW47 User Manual
Alinx Electronic Limited
Company Website: www.en.alinx.com
Service Hotline:+86 21 67676997
Technical Support : technical@alinx.com
Document Information
| Item | Content |
| Document Name | Product Manual |
| Product Model | ACW47 |
| Document Version | V1.0 |
| Prepared by | Alinx Electronic Limited |
| Release Date | 2026.9.28 |
Document Revision History
| Version | Date | Section | Revision Summary |
| V1.0 | 2026.9.28 | All | Initial Release |
Part 1 : SoM Introduction
The 47DR SoM is based on the Zynq UltraScale+ RFSoC series XCZU47DR-FFVE1156 (hereinafter referred to as XCZU47DR). This series integrates key subsystems of multi-band, multi-mode cellular radio and cable infrastructure (DOCSIS) into a single SoC platform, which includes a feature-rich 64-bit quad-core Arm® Cortex-A53 and dual-core Arm Cortex-R5F processing system.
The main chip, XCZU47DR, supports 8-channel 14-bit RF-ADC with a maximum sampling rate of 5 GSPS and 8-channel 14-bit RF-DAC with a maximum sampling rate of 9.85 GSPS. This reduces the complexity of the RF signal processing chain, maximizes input/output channel density without sacrificing bandwidth, utilizes heterogeneous processing capabilities, and boasts lower power consumption (eliminating ADC/DAC components and reducing FPGA-to-analog interface power consumption). Zynq UltraScale+ devices offer an ARM Cortex-A53 processing subsystem, UltraScale+ programmable logic, and the highest signal processing bandwidth, providing a comprehensive RF signal chain to meet the needs of wireless, cable TV access, test and measurement, early warning/radar, and other high-performance RF applications.
Product Overview
The 47DR SoM incorporates the AMD RFSoC in its most versatile design, enabling use across a wide range of scenarios. The SoM receives 12V power from the carrier board through boardtoboard connectors. The 47DR SoM uses six Micron DDR4 chips, model MT40A512M16LY062E IT:E. Four DDR4 chips are mounted on the PS side to form a 64bit data bus width, while two DDR4 chips are mounted on the PL side to form a 32bit data bus width. Each DDR4 chip has a capacity of 1GB. The DDR4 SDRAM supports data rates up to 3200 MT/s, and a 32GB eMMC is also provided. In addition, two 1Gbit NOR FLASH devices are integrated on the module for boot storage, configuration, and system files.
To interface with the carrier board, the module uses three 240pin boardtoboard connectors to expand: 2 HD Banks, 2 PS MIO Banks, 8× PL GTY (up to 28.21 Gb/s), 4× PS GTR (up to 6 Gb/s), 13 IOs (HP Bank), 8 highspeed RF ADCs, 8 highspeed DACs, and JTAG.
Application Scenarios
Product Features
The XCZU47DR FPGA chip integrates an RF direct sampling data converter, FPGA logic, a complete ARM processor subsystem, and a high-speed transceiver.
It supports 8 channels of 14-bit RF-ADC and 8 channels of 14-bit RF-DAC, providing a comprehensive RF signal chain to maximize input/output channel density, high bandwidth, heterogeneous processing capabilities, and low power consumption.
The product can meet the needs of different application scenarios, as well as the needs of high-performance RF applications.
Abundant information and resources: We provide complete board information and design resources, offer suggestions for secondary development, and continuously collect customer feedback to improve our support.
Collaborating with open-source projects: The board is among the first to partner with the MAGI Project, providing a wealth of flexible and configurable IPs to shorten customers' design and verification cycles.
Low cost and high cost performance: It has a lower price and more features compared to similar products.
High integration: leveraging MPSoC Its advantage lies in its ability to perform complex and heterogeneous tasks on-chip, which can significantly reduce debugging and development cycles compared to traditional multi-chip heterogeneous designs.
Appearance
The image below shows the appearance of the 47DR SoM. Currently, the product is being delivered as a board. We also provide accessory delivery services. If you require other accessories to be delivered together, please contact our sales team in advance.
Figure 1.4.1-47DR_SoM Appearance Diagram TOP
Figure 1.4.2-47DR_SoM Appearance Diagram BOTTOM
Part 2 : SoM Hardware Introduction
2.1 Board Block Diagram
The core hardware block diagram of 47DR is shown in the figure:
Figure 2.1.1-47DR_SoM Hardware Block Diagram
2.2 Key Parameters
The main chip of the SoM is XCZU47DR. The key parameters of the board are shown in the table below . (47DR_SoM Key Parameters)
| main chip | - XCZU47DR |
| size | - 90mm * 80.5mm |
| Expand memory | - PS DDR4 64-bit- PL DDR4 32-bit |
| storage | - Nor Flash 1Gbit *2 |
| eMMC | - PS eMMC 32 GB |
| indicator lights | - INIT_B and DONE are two working status indicator lights.- PS_ERR_OUT and PS_ERR_STATUS are two working status indicator lights. |
| Power supply for the board | The baseplate provides 12V power (via connector J4). |
| Power consumption | 60W (based on actual measured value, depending on the application) |
| Ambient temperature requirements | Operating temperature: -40℃ to 110℃ |
Table 2.2.1-47DR_SoM Key Parameters
2.3 Functions and Locations of the Board
The functions and locations of some parts of this board are shown in the figure below . The function description of each location is shown in Table 2.3.1, which shows the functions of each location on the SoM.
Figure 2.3.1-47DR_Core Functional Block Identification Diagram_TOP
Figure 2.3.2-47DR_Core Functional Block Identification Diagram_BOTTOM
| serial number | Function |
| 1 | Main chip, XCZU47DR, reference number U1. |
| 2 | PS DDR4 extended memory , up to 2400Mb/s, 64-bit bus width, total capacity 4GB. |
| 3 | PL DDR4 extended memory , up to 2400Mb/s, 32-bit bus width, total capacity 2GB. |
| 4 | LMK04828. |
| 5 | 100MHz crystal oscillator, LMK04828 OSCIN input clock. |
| 6 | QSPI Flash, 2Gbit capacity, stores code and data, U10 and U11. |
| 7 | Main chip operating status indicator, PS_ERR_OUT. |
| 8 | Main chip operating status indicator, PS_ERR_STATUS. |
| 9 | Main chip operating status indicator, PS_INIT_B. |
| 10 | Main chip operating status indicator, PS_DONE. |
| 11 | LMK04828 data output indicator. |
| 12 | LMK04828 Status LED. |
| 13 | 12V power supply is on and functioning normally. |
| 14 | Reset indicator light. |
| 15 | EMMC. |
| 16 | GTY BANK signal expansion interface, J4. |
| 17 | PS_MIO signal extension interface, J3. |
| 18 | RF expansion interface, J1. |
| 19 | 300MHz clock speed , used as the extended DDR4 operating clock reference. |
| 20 | 10MHz clock, LMK04828 OSCOUT input clock. |
Table 2.3.1-47DR_SoM Function Description
2.4 Startup Mode
The board has four boot modes: JTAG mode, QSPI mode, SD card mode, and EMMC mode. The boot mode of the XCZU47DR can be configured via a DIP switch (which needs to be reserved on the carrier board).
The main chip of this board, XCZU47DR (reference number U1), is an RFSoC FPGA. The boot mode is determined by the high/low states of four pins: PS_MODE0, PS_MODE1, PS_MODE2, and PS_MODE3. The board uses a four-position switch (reserved on the carrier board) to select the device configuration mode. Table 2.4.1 shows the configuration modes corresponding to each state of the XCZU47DR.
| BOOT mode | Mode pin [3:0] | SW[4:1] |
| JTAG | 0000 | ON, ON, ON, ON |
| QSPI | 0010 | ON, ON, OFF, ON |
| eMMC | 0110 | ON, OFF, OFF, ON |
| SD | 0101 | ON, OFF, ON, OFF |
Table 2.4.1 - Correspondence of Mode Pins on the PS Terminal of XCZU47DR
2.5 DDR4 memory
As shown in the 47DR SoM hardware block diagram, the main chip XCZU47DR of this board is configured with two sets of DDR4 extended memory. Four DDR4 chips are installed on the PS side to form a 64-bit data bus width, and two DDR4 chips are installed on the PL side to form a 32-bit data bus width. It consists of six Micron MT40A512M16LY-062E IT:E chips. A 300MHz differential crystal oscillator is used as the reference clock. The specific DDR4 configuration on the PS and PL sides is shown in the table below :
| Location | Position | Chip Model | capacity | factory |
| PS | U24, U25, U26, U27 | MT40A512M16LY-062E IT:E | 512x16bit | Micron |
| PL | U28, U29 | MT40A512M16LY-062E IT:E | 512x16bit | Micron |
Table 2.5.1 - DDR4 Configuration
The hardware connection method for DDR4 on the PS side is shown in the following figure:
Figure 2.5.1 - Schematic diagram of DDR4 connection on the PS side
The hardware connection method for DDR4 on the PL side is as follows:
Figure 2.5.2 - Schematic diagram of DDR4 connection at the PL end
Notice:
While memory chips support transfer rates up to 3200 MT/s, FPGA chips support a maximum transfer rate of 2400 Mb/s. Please refer to the chip datasheet for details.
This section shows the highest performance parameters for the memory and main chip (which also means the highest power consumption). Users can adjust these parameters according to their usage scenarios to balance power consumption and performance .
2.6 QSPI FLASH
The board is equipped with two MT25QU01GBBB8E12-0SIT serial Nor Flash memory chips in the PS, which can be used to store executable code and data, such as bootloaders, operating systems, and bitstreams. The two QSPI chips are connected in parallel.
To achieve higher performance, two Quad-SPI devices are connected in parallel, providing a total of 8 bits of data bus for booting and configuration. The XCZU47DR is connected to two QSPI Nor Flash chips , as shown below:
Figure 2.6.1 - Schematic diagram of interconnection between two QSPI Nor Flash chips and XCZU47DR
The interconnect pin definitions for the two QSPI Nor Flash chips are as follows :
| FPGA pin numbers | FPGA pin names | signal name | QSPI pin numbers | QSPI pin names |
| U1.MIO12_B15 | PS_MIO12_B15 | MIO12_QSPI_UPR_CLK | U11.B2 | C |
| U1.MIO10_C15 | PS_MIO10_C15 | MIO10_QSPI_UPR_DQ2 | U11.C4 | DQ2_W_B |
| U1.MIO9_F15 | PS_MIO9_F15 | MIO9_QSPI_UPR_DQ1 | U11.D2 | DQ1 |
| U1.MIO8_E15 | PS_MIO8_E15 | MIO8_QSPI_UPR_DQ0 | U11.D3 | DQ0 |
| U1. MIO11_G16 | PS_MIO11_G16 | MIO11_QSPI_UPR_DQ3 | U11.D4 | DQ3_RST_HLD_B |
| U1.MIO7_K17 | PS_MIO7_K17 | MIO7_QSPI_UPR_CS_B | U11.C2 | S_B |
| U1.MIO5_H18 | PS_MIO5_H18 | MIO5_QSPI_LWR_CS_B | U10.C2 | S_B |
| U1.MIO4_G15 | PS_MIO4_G15 | MIO4_QSPI_LWR_DQ0 | U10.D3 | DQ0 |
| U1.MIO3_K16 | PS_MIO3_K16 | MIO3_QSPI_LWR_DQ3 | U10.D4 | DQ3_RST_HLD_B |
| U1.MIO2_J16 | PS_MIO2_J16 | MIO2_QSPI_LWR_DQ2 | U10.C4 | DQ2_W_B |
| U1.MIO1_J18 | PS_MIO1_J18 | MIO1_QSPI_LWR_DQ1 | U10.D2 | DQ1 |
| U1.MIO0_J17 | PS_MIO0_J17 | MIO0_QSPI_LWR_CLK | U10.B2 | C |
Table 2.6.1 - Interconnect Pin Definitions for Two QSPI Nor Flash Chips
2.7 eMMC
The SoM provides eMMC storage. It connects to the PS terminal of the main chip and interacts directly with the main chip.
The overall connection diagram of eMMC is shown in the figure below:
Figure 2.7.1 - Overall connection diagram of eMMC
eMMC Pin Assignment Table:
| Signal name | pin name | pin number |
| eMMC_DS | PS_MIO25_B17 | B17 |
| MIO23_eMMC_RST | PS_MIO23_D17 | D17 |
| MIO22_eMMC_CLK | PS_MIO22_E17 | E17 |
| MIO21_eMMC_CMD | PS_MIO21_F17 | F17 |
| MIO20_eMMC_DAT7 | PS_MIO20_B16 | B16 |
| MIO20_eMMC_DAT6 | PS_MIO19_C16 | C16 |
| MIO18_eMMC_DAT5 | PS_MIO18_F18 | F18 |
| MIO17_eMMC_DAT4 | PS_MIO17_E16 | E16 |
| MIO16_eMMC_DAT3 | PS_MIO16_G17 | G17 |
| MIO15_eMMC_DAT2 | PS_MIO15_D16 | D16 |
| MIO14_eMMC_DAT1 | PS_MIO14_A15 | A15 |
| MIO13_eMMC_DAT0 | PS_MIO13_G18 | G18 |
Table 2.7.1 - eMMC Pin Assignment
2.8 EEPROM
The SoM features an onboard EEPROM, model M24C08-RDW6TP, with a capacity of 8Kb, which communicates with the PL terminal via the IIC bus. EEPROM pin assignment table:
| Signal name | pin name | pin number | Remark |
| IIC_EEPROM_SCL | IO_L12N_AD8N_88_A12 | A12 | I2C clock signal |
| IIC_EEPROM_SDA | IO_L12P_AD8P_88_B12 | B12 | I2C data signal |
Table 2.8.1 - EEPROM Pin Definitions
2.9 SoM Indicator Lights
Main chip status indicator:
The main chip XCZU47DR (reference number U1) on this board has 8 status indicator lights . The positions of the FPGA status indicator lights are shown in the following figure , and the position diagram of the main chip XCZU47DR status indicator lights is also shown:
Figure 2.9.1 - Schematic diagram of the location of status indicator lights on the main chip XCZU47DR
The functional status indicated by each LED is shown in the following table, XCZU47DR Status Indicator Function Description:
| LED number | Indicator light color | Function |
| DS1 | red | FPGA initialization error |
| DS2 | red | FPGA download error |
| DS3 | red | PS_ERR_OUT indicator light |
| DS4 | red | PS_ERR_STATUS indicator light |
Table 2.9.1 - Function Description of Status Indicator Lights on Main Chip XCZU47DR
Power indicator light for the entire board:
This board requires a 12V input power supply, provided by the carrier board and introduced to the SoM via connector J4. When the input power is normal, the power indicator DS6 will be highlighted green. The DS6 indicator is located at position 13. A schematic diagram of the DS6 power indicator's location is shown in the following figure:
Figure 2.9.2 - Schematic diagram of the location of power indicator DS6 at position 13.
2.10 PS - GTR Interface
The PS-side GTR high-speed BANK on the SoM is not used at all; it is all pulled out through the connector. It supports a maximum data rate of 6.0Gb/s and can be used as a PCIe Gen2 x1, x2, or x4 port, or as a SATA port, supporting data rates of 1.5Gb/s, 3.0Gb/s, and 6Gb/s. It can also support DP interfaces, USB 3.0 interfaces, and other applications.
Figure 2.10.1 - Mapping diagram of GTR high-speed transceiver at PS end
2.11 PS - GTY Interface
The SoM supports the GTY high-speed transceiver, which enables PCIe x8 Gen4.0 (requires a PCIe carrier card) with data rates up to 16.0Gb/s. It also supports 100G fiber optic interface interconnection . This facilitates secondary development by users, minimizes design risks, and offers flexibility.
Figure 2.11.1 - High-speed transceiver mapping diagram
2.12 RF Interface
The FPGA chip used in the SoM is the Zynq™ UltraScale+™ RFSoC Gen3 series, the industry's only single-chip adaptive radio platform. The chip integrates a 14-bit RF-ADC with a maximum sampling rate of 5GSPS, and the VCM signal is also brought out to the connector for easy adjustment of the common-mode voltage.
Figure 2.12.1 - RF-ADC Interface Diagram
The core component uses an FPGA chip, the Zynq™ UltraScale+™ RFSoC Gen3 series, which is the industry's only single-chip adaptive radio platform. The chip integrates a 14-bit RF-DAC with a maximum sampling rate of 9.85 GSPS.
Figure 2.12.2- RF-DAC Interface Diagram
2.13 Clock Configuration
The SoM provides dual crystal clocks, with the system clock using a 33.3333MHz active crystal oscillator by default. The crystal operates at 32.768kHz and drives the internal RTC circuitry of the SoM. A schematic diagram of the clock circuit design is shown below:
Figure 2.13.1 - Crystal Oscillator Schematic Diagram
The SoM uses the LMK04828 clock chip to distribute the clock required by each module, and the main crystal oscillator is a 100MHz crystal oscillator. It supports GTY clock recovery, external reference clock input, and SYSREF input, and can realize the parallel connection of multiple modules to form a larger-scale coherent RF channel .
Figure 2.13.2 - Schematic diagram of the overall clock topology
2.14 Power Supply
The SoM is powered by 12V DC, supplied via a connector backplane. The typical power consumption of the SoM is 60W . The 12V system power supply is converted into different voltages by a buck regulator to drive the FPGA and other circuits on the board. The ADC and DAC on the board are powered by a linear low-voltage LDO, which has good power supply rejection (PSRR).
The extended IO BANK interface levels of the core module are as follows :
| BANK | Level | Remark |
| BANK65 | 1.2V | Without any definition, the remaining I/O is pulled to the connector. |
| BANK88 | 3.3V | HD_BANK supports 1.2~3.3V (HD I/O only) at ±5% |
| BANK89 | 1.8V or 3.3V | The SoM defaults to 1.8V, and the bank level can be adjusted using a ferrite bead. |
| BANK128 | MGTY (1.2V) | PCIe Gen4 signal |
| BANK129 | MGTY (1.2V) | PCIe Gen4 signal |
| BANK501 | 1.8V or 3.3V | The SoM defaults to 1.8V, and the bank level can be adjusted using a ferrite bead. |
| BANK502 | 1.8V or 3.3V | The SoM defaults to 1.8V, and the bank level can be adjusted using a ferrite bead. |
| BANK503 | 1.8V fixed | Configure pin outputs, mode selection, and system reset signal. |
| BANK505 | PS_MGTR | Without any definition, all high-speed signal pins and clock signals are pulled out to the connector. |
Table 2.14.1 - Main Chip XCZU47DR IO BANK Level Description
Figure 2.14.1 - Overall power supply structure tree
2.15 Structural Diagram
Figure 2.15.1 - Front view of the core plate
2.16 User Extension Interface Definition
The SoM has three high-speed expansion ports, connected to the carrier board via 240-pin inter-board connectors (J1, J3, J4). The connectors used are Samtec ADM6-60-01.5-L-4-2-TR connectors. The connector signal definitions are as follows:
J1 connector definition:
| label | Signal Network | label | Signal Network | label | Signal Network | label | Signal Network |
| A01 | GND | B01 | GND | C01 | GND | D01 | GND |
| A02 | GND | B02 | GND | C02 | GND | D02 | GND |
| A03 | GND | B03 | GND | C03 | GND | D03 | GND |
| A04 | GND | B04 | GND | C04 | GND | D04 | GND |
| A05 | GND | B05 | GND | C05 | GND | D05 | GND |
| A06 | VCM01_224 | B06 | VCM01_225 | C06 | VCM01_226 | D06 | VCM01_227 |
| A07 | GND | B07 | GND | C07 | GND | D07 | GND |
| A08 | GND | B08 | GND | C08 | GND | D08 | GND |
| A09 | GND | B09 | GND | C09 | GND | D09 | GND |
| A10 | GND | B10 | GND | C10 | GND | D10 | GND |
| A11 | VCM23_224 | B11 | VCM23_225 | C11 | VCM23_226 | D11 | VCM23_227 |
| A12 | GND | B12 | GND | C12 | GND | D12 | GND |
| A13 | GND | B13 | GND | C13 | GND | D13 | GND |
| A14 | GND | B14 | GND | C14 | GND | D14 | GND |
| A15 | GND | B15 | GND | C15 | GND | D15 | GND |
| A16 | RFMC_ADC_01_N | B16 | RFMC_ADC_01_P | C16 | RFMC_ADC_00_N | D16 | RFMC_ADC_00_P |
| A17 | GND | B17 | GND | C17 | GND | D17 | GND |
| A18 | GND | B18 | GND | C18 | GND | D18 | GND |
| A19 | GND | B19 | GND | C19 | GND | D19 | GND |
| A20 | GND | B20 | GND | C20 | GND | D20 | GND |
| A21 | RFMC_ADC_03_N | B21 | RFMC_ADC_03_P | C21 | RFMC_ADC_02_N | D21 | RFMC_ADC_02_P |
| A22 | GND | B22 | GND | C22 | GND | D22 | GND |
| A23 | GND | B23 | GND | C23 | GND | D23 | GND |
| A24 | GND | B24 | GND | C24 | GND | D24 | GND |
| A25 | GND | B25 | GND | C25 | GND | D25 | GND |
| A26 | RFMC_ADC_05_N | B26 | RFMC_ADC_05_P | C26 | RFMC_ADC_04_N | D26 | RFMC_ADC_04_P |
| A27 | GND | B27 | GND | C27 | GND | D27 | GND |
| A28 | GND | B28 | GND | C28 | GND | D28 | GND |
| A29 | GND | B29 | GND | C29 | GND | D29 | GND |
| A30 | GND | B30 | GND | C30 | GND | D30 | GND |
| A31 | RFMC_ADC_07_N | B31 | RFMC_ADC_07_P | C31 | RFMC_ADC_06_N | D31 | RFMC_ADC_06_P |
| A32 | GND | B32 | GND | C32 | GND | D32 | GND |
| A33 | GND | B33 | GND | C33 | GND | D33 | GND |
| A34 | GND | B34 | GND | C34 | GND | D34 | GND |
| A35 | GND | B35 | GND | C35 | GND | D35 | GND |
| A36 | RFMC_DAC_04_N | B36 | RFMC_DAC_04_P | C36 | RFMC_DAC_00_N | D36 | RFMC_DAC_00_P |
| A37 | GND | B37 | GND | C37 | GND | D37 | GND |
| A38 | GND | B38 | GND | C38 | GND | D38 | GND |
| A39 | GND | B39 | GND | C39 | GND | D39 | GND |
| A40 | GND | B40 | GND | C40 | GND | D40 | GND |
| A41 | RFMC_DAC_05_N | B41 | RFMC_DAC_05_P | C41 | RFMC_DAC_01_N | D41 | RFMC_DAC_01_P |
| A42 | GND | B42 | GND | C42 | GND | D42 | GND |
| A43 | GND | B43 | GND | C43 | GND | D43 | GND |
| A44 | GND | B44 | GND | C44 | GND | D44 | GND |
| A45 | GND | B45 | GND | C45 | GND | D45 | GND |
| A46 | RFMC_DAC_06_N | B46 | RFMC_DAC_06_P | C46 | RFMC_DAC_02_N | D46 | RFMC_DAC_02_P |
| A47 | GND | B47 | GND | C47 | GND | D47 | GND |
| A48 | GND | B48 | GND | C48 | GND | D48 | GND |
| A49 | GND | B49 | GND | C49 | GND | D49 | GND |
| A50 | GND | B50 | GND | C50 | GND | D50 | GND |
| A51 | RFMC_DAC_07_N | B51 | RFMC_DAC_07_P | C51 | RFMC_DAC_03_N | D51 | RFMC_DAC_03_P |
| A52 | GND | B52 | GND | C52 | GND | D52 | GND |
| A53 | GND | B53 | GND | C53 | GND | D53 | GND |
| A54 | GND | B54 | GND | C54 | GND | D54 | GND |
| A55 | GND | B55 | GND | C55 | GND | D55 | GND |
| A56 | GND | B56 | GND | C56 | GND | D56 | GND |
| A57 | GND | B57 | GND | C57 | GND | D57 | GND |
| A58 | GND | B58 | GND | C58 | GND | D58 | GND |
| A59 | GND | B59 | GND | C59 | GND | D59 | GND |
| A60 | GND | B60 | GND | C60 | GND | D60 | GND |
Table 2.16.1 - Signal Interconnection Table between Expansion Interface J1 and Main Chip
J3 connector definition:
| label | Signal Network | label | Signal Network | label | Signal Network | label | Signal Network |
| A01 | GND | B01 | GND | C01 | GND | D01 | GND |
| A02 | GND | B02 | GND | C02 | GND | D02 | GND |
| A03 | GND | B03 | GND | C03 | GND | D03 | GND |
| A04 | GND | B04 | GND | C04 | GND | D04 | GND |
| A05 | CLKIN0_P | B05 | CLKIN0_N | C05 | CLKIN1_P | D05 | CLKIN1_N |
| A06 | GND | B06 | GND | C06 | GND | D06 | GND |
| A07 | GND | B07 | GND | C07 | GND | D07 | GND |
| A08 | GND | B08 | GND | C08 | IO_L2P_T0L_N2_66_AP6_1V2 | D08 | IO_L2N_T0L_N3_66_AP5_1V2 |
| A09 | GND | B09 | IO_T3U_N12_66_AH12_1V2 | C09 | GND | D09 | GND |
| A10 | GND | B10 | GND | C10 | IO_L3P_T0L_N4_AD15P_66_AM6_1V2 | D10 | IO_L3N_T0L_N5_AD15N_66_AM5_1V2 |
| A11 | VCC_PSBATT_C | B11 | PS_DONE | C11 | GND | D11 | GND |
| A12 | GND | B12 | GND | C12 | GND | D12 | PS_ERR_OUT |
| A13 | GND | B13 | GND | C13 | GND | D13 | GND |
| A14 | JTAG_TDO | B14 | GND | C14 | IO_L5P_T0U_N8_AD14P_66_AP3_1V2 | D14 | IO_L5N_T0U_N9_AD14N_66_AP2_1V2 |
| A15 | GND | B15 | PS_INIT_B | C15 | GND | D15 | GND |
| A16 | GND | B16 | GND | C16 | PS_ERR_STATUS | D16 | PS_PROG_B |
| A17 | GND | B17 | GND | C17 | GND | D17 | GND |
| A18 | PS_POR_B | B18 | PS_SRST_B | C18 | GND | D18 | GND |
| A19 | GND | B19 | GND | C19 | IO_L1P_T0L_N0_DBC_66_AP8_1V2 | D19 | IO_L1N_T0L_N1_DBC_66_AP7_1V2 |
| A20 | JTAG_TCK | B20 | JTAG_TMS | C20 | GND | D20 | GND |
| A21 | GND | B21 | GND | C21 | IO_L6P_T0U_N10_AD6P_66_AN2_1V2 | D21 | IO_L6N_T0U_N11_AD6N_66_AN1_1V2 |
| A22 | IO_L4P_T0U_N6_DBC_AD7P_66_AN5_1V2 | B22 | IO_L4N_T0U_N7_DBC_AD7N_66_AN4_1V2 | C22 | GND | D22 | GND |
| A23 | GND | B23 | GND | C23 | GND | D23 | GND |
| A24 | PS_MODE3 | B24 | JTAG_TDI | C24 | GND | D24 | GND |
| A25 | GND | B25 | GND | C25 | PS_MODE2 | D25 | LMK_SYNC_C |
| A26 | PS_MODE1 | B26 | PS_MODE0 | C26 | GND | D26 | GND |
| A27 | GND | B27 | GND | C27 | GND | D27 | GND |
| A28 | GND | B28 | GND | C28 | BANK505_MGT_RX0_P | D28 | BANK505_MGT_RX0_N |
| A29 | BANK505_MGT_CLK0_P | B29 | BANK505_MGT_CLK0_N | C29 | GND | D29 | GND |
| A30 | GND | B30 | GND | C30 | BANK505_MGT_RX1_P | D30 | BANK505_MGT_RX1_N |
| A31 | BANK505_MGT_TX0_P | B31 | BANK505_MGT_TX0_N | C31 | GND | D31 | GND |
| A32 | GND | B32 | GND | C32 | BANK505_MGT_RX2_P | D32 | BANK505_MGT_RX2_N |
| A33 | BANK505_MGT_TX1_P | B33 | BANK505_MGT_TX1_N | C33 | GND | D33 | GND |
| A34 | GND | B34 | GND | C34 | BANK505_MGT_RX3_P | D34 | BANK505_MGT_RX3_N |
| A35 | BANK505_MGT_TX2_P | B35 | BANK505_MGT_TX2_N | C35 | GND | D35 | GND |
| A36 | GND | B36 | GND | C36 | BANK505_MGT_CLK1_P | D36 | BANK505_MGT_CLK1_N |
| A37 | BANK505_MGT_CLK2_P | B37 | BANK505_MGT_CLK2_N | C37 | GND | D37 | GND |
| A38 | GND | B38 | GND | C38 | BANK505_MGT_CLK3_P | D38 | BANK505_MGT_CLK3_N |
| A39 | BANK505_MGT_TX3_P | B39 | BANK505_MGT_TX3_N | C39 | GND | D39 | GND |
| A40 | GND | B40 | GND | C40 | BANK128_MGT_RX0_P | D40 | BANK128_MGT_RX0_N |
| A41 | BANK128_MGT_TX0_P | B41 | BANK128_MGT_TX0_N | C41 | GND | D41 | GND |
| A42 | GND | B42 | GND | C42 | BANK128_MGT_CLK1_P | D42 | BANK128_MGT_CLK1_N |
| A43 | BANK128_MGT_TX1_P | B43 | BANK128_MGT_TX1_N | C43 | GND | D43 | GND |
| A44 | GND | B44 | GND | C44 | BANK128_MGT_RX1_P | D44 | BANK128_MGT_RX1_N |
| A45 | BANK129_MGT_CLK1_P | B45 | BANK129_MGT_CLK1_N | C45 | GND | D45 | GND |
| A46 | GND | B46 | GND | C46 | BANK128_MGT_RX2_P | D46 | BANK128_MGT_RX2_N |
| A47 | BANK128_MGT_TX2_P | B47 | BANK128_MGT_TX2_N | C47 | GND | D47 | GND |
| A48 | GND | B48 | GND | C48 | BANK128_MGT_RX3_P | D48 | BANK128_MGT_RX3_N |
| A49 | BANK128_MGT_TX3_P | B49 | BANK128_MGT_TX3_N | C49 | GND | D49 | GND |
| A50 | GND | B50 | GND | C50 | BANK129_MGT_RX0_P | D50 | BANK129_MGT_RX0_N |
| A51 | BANK129_MGT_TX0_P | B51 | BANK129_MGT_TX0_N | C51 | GND | D51 | GND |
| A52 | GND | B52 | GND | C52 | BANK129_MGT_RX1_P | D52 | BANK129_MGT_RX1_N |
| A53 | BANK129_MGT_TX1_P | B53 | BANK129_MGT_TX1_N | C53 | GND | D53 | GND |
| A54 | GND | B54 | GND | C54 | BANK129_MGT_RX2_P | D54 | BANK129_MGT_RX2_N |
| A55 | BANK129_MGT_TX2_P | B55 | BANK129_MGT_TX2_N | C55 | GND | D55 | GND |
| A56 | GND | B56 | GND | C56 | BANK129_MGT_RX3_P | D56 | BANK129_MGT_RX3_N |
| A57 | BANK129_MGT_TX3_P | B57 | BANK129_MGT_TX3_N | C57 | GND | D57 | GND |
| A58 | GND | B58 | GND | C58 | GND | D58 | GND |
| A59 | GND | B59 | GND | C59 | GND | D59 | GND |
| A60 | GND | B60 | GND | C60 | GND | D60 | GND |
Table 2.16.2 - Signal Interconnection Table between Expansion Interface J3 and Main Chip
J4 connector definition:
| label | Signal Network | label | Signal Network | label | Signal Network | label | Signal Network |
| A01 | VCC12V_SW | B01 | VCC12V_SW | C01 | VCC12V_SW | D01 | VCC12V_SW |
| A02 | VCC12V_SW | B02 | VCC12V_SW | C02 | VCC12V_SW | D02 | VCC12V_SW |
| A03 | VCC12V_SW | B03 | VCC12V_SW | C03 | VCC12V_SW | D03 | VCC12V_SW |
| A04 | VCC12V_SW | B04 | VCC12V_SW | C04 | VCC12V_SW | D04 | VCC12V_SW |
| A05 | GND | B05 | GND | C05 | GND | D05 | GND |
| A06 | GND | B06 | GND | C06 | GND | D06 | GND |
| A07 | GND | B07 | GND | C07 | GND | D07 | GND |
| A08 | GND | B08 | GND | C08 | DXP | D08 | DXN |
| A09 | BANK501_PS_MIO28 | B09 | GND | C09 | GND | D09 | GND |
| A10 | GND | B10 | GND | C10 | BANK502_PS_MIO66 | D10 | BANK502_PS_MIO67 |
| A11 | BANK501_PS_MIO29 | B11 | BANK501_PS_MIO30 | C11 | GND | D11 | GND |
| A12 | GND | B12 | GND | C12 | BANK502_PS_MIO68 | D12 | BANK502_PS_MIO76 |
| A13 | BANK501_PS_MIO33 | B13 | BANK501_PS_MIO31 | C13 | GND | D13 | GND |
| A14 | GND | B14 | GND | C14 | BANK502_PS_MIO69 | D14 | BANK502_PS_MIO77 |
| A15 | BANK501_PS_MIO35 | B15 | BANK501_PS_MIO32 | C15 | GND | D15 | GND |
| A16 | GND | B16 | GND | C16 | BANK502_PS_MIO72 | D16 | BANK502_PS_MIO74 |
| A17 | BANK501_PS_MIO49 | B17 | BANK501_PS_MIO42 | C17 | GND | D17 | GND |
| A18 | GND | B18 | GND | C18 | BANK502_PS_MIO70 | D18 | BANK502_PS_MIO75 |
| A19 | BANK501_PS_MIO47 | B19 | BANK501_PS_MIO50 | C19 | GND | D19 | GND |
| A20 | GND | B20 | GND | C20 | BANK502_PS_MIO73 | D20 | BANK502_PS_MIO64 |
| A21 | BANK501_PS_MIO48 | B21 | BANK501_PS_MIO51 | C21 | GND | D21 | GND |
| A22 | GND | B22 | GND | C22 | BANK502_PS_MIO65 | D22 | BANK502_PS_MIO71 |
| A23 | BANK501_PS_MIO44 | B23 | BANK501_PS_MIO45 | C23 | GND | D23 | GND |
| A24 | GND | B24 | GND | C24 | BANK502_PS_MIO54 | D24 | BANK502_PS_MIO56 |
| A25 | BANK501_PS_MIO46 | B25 | BANK501_PS_MIO39 | C25 | GND | D25 | GND |
| A26 | GND | B26 | GND | C26 | BANK502_PS_MIO60 | D26 | BANK502_PS_MIO62 |
| A27 | BANK501_PS_MIO41 | B27 | BANK501_PS_MIO43 | C27 | GND | D27 | GND |
| A28 | GND | B28 | GND | C28 | BANK502_PS_MIO63 | D28 | BANK502_PS_MIO58 |
| A29 | BANK501_PS_MIO27 | B29 | BANK501_PS_MIO26 | C29 | GND | D29 | GND |
| A30 | GND | B30 | GND | C30 | BANK502_PS_MIO59 | D30 | BANK502_PS_MIO55 |
| A31 | BANK501_PS_MIO40 | B31 | BANK501_PS_MIO38 | C31 | GND | D31 | GND |
| A32 | GND | B32 | GND | C32 | BANK502_PS_MIO61 | D32 | BANK501_PS_MIO37 |
| A33 | BANK501_PS_MIO36 | B33 | BANK500_PS_MIO24 | C33 | GND | D33 | GND |
| A34 | GND | B34 | GND | C34 | BANK502_PS_MIO57 | D34 | BANK502_PS_MIO52 |
| A35 | BANK501_PS_MIO34 | B35 | BANK500_PS_MIO6 | C35 | GND | D35 | GND |
| A36 | GND | B36 | GND | C36 | BANK502_PS_MIO53 | D36 | GND |
| A37 | GND | B37 | GND | C37 | GND | D37 | GND |
| A38 | GND | B38 | GND | C38 | GND | D38 | BANK88_IO_GC_L5N |
| A39 | BANK89_IO_L10P | B39 | BANK89_IO_L10N | C39 | GND | D39 | GND |
| A40 | GND | B40 | GND | C40 | BANK89_IO_L12P | D40 | BANK89_IO_L12N |
| A41 | BANK89_IO_L9P | B41 | BANK89_IO_L9N | C41 | GND | D41 | GND |
| A42 | GND | B42 | GND | C42 | BANK89_IO_L11P | D42 | BANK89_IO_L11N |
| A43 | BANK89_IO_GC_L8P | B43 | BANK89_IO_GC_L8N | C43 | GND | D43 | GND |
| A44 | GND | B44 | GND | C44 | BANK88_IO_GC_L6P | D44 | BANK88_IO_GC_L6N |
| A45 | GND | B45 | GND | C45 | GND | D45 | GND |
| A46 | GND | B46 | GND | C46 | BANK88_IO_GC_L7P | D46 | BANK88_IO_GC_L7N |
| A47 | BANK89_IO_GC_L7P | B47 | BANK89_IO_GC_L7N | C47 | GND | D47 | GND |
| A48 | GND | B48 | GND | C48 | BANK88_IO_L9P | D48 | BANK88_IO_L9N |
| A49 | BANK89_IO_GC_L5P | B49 | BANK89_IO_GC_L5N | C49 | GND | D49 | GND |
| A50 | GND | B50 | GND | C50 | BANK88_IO_L10P | D50 | BANK88_IO_L10N |
| A51 | BANK89_IO_L4P | B51 | BANK89_IO_L4N | C51 | GND | D51 | GND |
| A52 | GND | B52 | GND | C52 | BANK88_IO_L11P | D52 | BANK88_IO_L11N |
| A53 | BANK89_IO_L2P | B53 | BANK89_IO_L2N | C53 | GND | D53 | GND |
| A54 | GND | B54 | GND | C54 | BANK88_IO_GC_L8P | D54 | BANK88_IO_GC_L8N |
| A55 | BANK89_IO_L3P | B55 | BANK89_IO_L3N | C55 | GND | D55 | GND |
| A56 | GND | B56 | GND | C56 | BANK89_IO_L1P | D56 | BANK89_IO_L1N |
| A57 | BANK89_IO_GC_L6P | B57 | BANK89_IO_GC_L6N | C57 | GND | D57 | GND |
| A58 | GND | B58 | GND | C58 | GND | D58 | GND |
| A59 | GND | B59 | GND | C59 | GND | D59 | GND |
| A60 | GND | B60 | GND | C60 | GND | D60 | GND |
Table 2.16.3 - Signal Interconnection Table between Expansion Interface J4 and Main Chip
Appendix: List of Abbreviations
Contact information
Alinx Electronic Limited
Company Website: www.en.alinx.com
Service Hotline: +86 21 67676997
Technical Support:technical@alinx.com