ACRF49 User Manual

　　Alinx Electronic Limited

Company Website: www.en.alinx.com

Service Hotline: +86 21 67676997

Technical Support : technical@alinx.com

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Document Information

Item	Content
Document Name	Product Manual
Product Model	ACRF49
Document Version	V1.0
Prepared by	Alinx Electronic Limited
Release Date	2026.9.30

Document Revision History

Version	Date	Section	Revision Summary
V1.0	2026.9.30	All	Initial Release

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Part 1：ACRF49 SoM

1.1 ACRF49 SoM Introduction

The Zynq chip on the ACRF49 SoM is based on Xilinx's Zynq UltraScale+ RFSoC Gen3 series ZU49DR-2FSVF1760I.

The ACRF49 SoM is equipped with ten Micron DDR4 chips (MT40A512M16). Five DDR4 chips are connected to the PS side, forming a 64-bit data bus with ECC support, while the remaining five DDR4 chips are connected to the PL side, forming a 72-bit data bus. Each DDR4 chip has a capacity of 1 GB. The maximum operating frequency of the DDR4 SDRAM is up to 1333 MHz (corresponding to a data rate of 2666 Mbps). In addition, the SoM integrates a 1 Gbit QSPI Flash for boot configuration and system file storage.

To interface with the carrier board, the ACRF49 SoM features three 800-pin high-speed board-to-board connectors. These connectors provide access to PS-side interfaces including USB 3.0, Gigabit Ethernet, SD card, M.2, DisplayPort (DP), and the remaining MIO signals, as well as PL-side interfaces including two QSFP28 ports, one FMC+ expansion interface, and additional user expansion I/O signals.

Figure1.1.1-ACRF49 SoM (Front View)

Figure1.1.2-ACRF49 SoM (Back View)

1.2 MPSOC Chip

The ACRF49 SoM is based on the Xilinx Zynq UltraScale+ RFSoC Gen3 series chip, model ZU49DR-2FSVF1760I. The programmable logic (PL) section provides abundant FPGA resources for high-throughput digital signal processing (DSP) and supports a wide range of IP cores, including digital up/down conversion (DUC/DDC) kernels. FPGA acceleration can be efficiently implemented through software-defined radio (SDR) development frameworks, application programming interfaces (APIs), and FPGA infrastructure, enabling rapid system development and allowing users to focus on value-added IP design. Pre-validated FPGA functions such as Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filters provide an excellent starting point, while custom IP blocks can be seamlessly integrated into the modular architecture using the user’s preferred hardware description language (HDL).

In addition to the FPGA fabric, the Xilinx UltraScale+ RFSoC integrates four application processing units (APUs) and two real-time processing units (RPUs), making it well suited for applications that require an embedded operating system and independent system operation.

Figure1.2.1- RFSOM Hardware System Block Diagram

1.3 DDR4 DRAM

The ACRF49 SoM is equipped with ten Micron 1 GB DDR4 chips, model MT40A512M16LY-075E. Five DDR4 chips are connected to the PS side, forming a 64-bit data bus with ECC support, while the remaining five DDR4 chips are connected to the PL side, forming a 72-bit data bus.

The PS-side DDR4 SDRAM operates at a maximum clock frequency of 1200 MHz (data rate of 2400 Mbps), with the five DDR4 memory chips directly interfaced to the PS BANK 504 memory controller. The PL-side DDR4 SDRAM operates at a maximum clock frequency of 1333 MHz (data rate of 2666 Mbps), with the five DDR4 chips connected to the FPGA BANKs 67, 68, and 69.

The detailed configurations of the PS-side and PL-side DDR4 SDRAM are summarized in Table 1.3.1.

Position	Reference	Part number	Form	Factory
PS	UM1,UM2,UM5,UM6,UM9	MT40A512M16LY-075E	512x16bit	Micron
PL	UM3,UM4,UM7,UM8,UM10	MT40A512M16LY-075E	512x16bit	Micron

Table1.3.1- DDR4 SDRAM Configuration

The hardware connection method for the PS-side DDR4 is shown in Figure 1.3.1:

Figure 1.3.1-PS DDR4 DRAM block diagram

The hardware connection method for the PL-side DDR4 SDRAM is shown in Figure 1.3.2:

Figure1.3.2-PL DDR4 DRAM block diagram

1.4 QSPI Flash

The ACRF49 SoM integrates two 512 Mbit Quad-SPI (QSPI) Flash chips, forming an 8-bit data bus. The Flash device model is MT25QU512ABBIEW9-0SIT and operates at a 1.8 V CMOS voltage standard. Due to the non-volatile nature of QSPI Flash memory, it can be used as the system boot device for storing boot images. These images primarily include FPGA configuration bitstreams, ARM application code, and user data files. The detailed model information and key characteristics of the QSPI Flash are listed in Table 1.4.1.

Position	Reference	Part number	Capacity	Factory
PS	U6,U7	MT25QU512ABBIEW9-0SIT	512Mbit	Micron

Table 1.4.1- QSPI FLASH Specification

The QSPI FLASH is connected to the MIO of BANK500 on the ZYNQ chip's PS side. In system design, these MIO functions on the PS side need to be configured as QSPI FLASH interfaces.

Figure1.4.1 shows the QSPI Flash in the schematic.

Figure1.4.1- QSPI Flash in the schematic

Configure chip pin assignments:

Signal Name	Pin Name	Pin Number
SPIL_SCLK	PS_MIO0	BB27
SPIL_MO1	PS_MIO1	BA27
SPIL_MO2	PS_MIO2	BB26
SPIL_MO3	PS_MIO3	BB28
SPIL_MO0	PS_MIO4	BA28
SPIL_CS	PS_MIO5	BA29
SPIH_CS	PS_MIO7	AY27
SPIH_MO0	PS_MIO8	AW27
SPIH_MO1	PS_MIO9	AW26
SPIH_MO2	PS_MIO10	AV26
SPIH_MO3	PS_MIO11	AW28
SPIH_SCLK	PS_MIO12	AV28

Table 1.4.2- QSPI Flash chip pin assignment

1.5 eMMC Flash

The ACRF49 SoM is equipped with one 8 GB eMMC Flash chip, model MTFC8GLVEA-1MWT, supporting a 1.8 V voltage standard. The data bus width between the eMMC Flash and the Zynq chip is 8 bits. Owing to its large capacity and non-volatile nature, the eMMC Flash serves as a high-capacity storage device within the Zynq system and is typically used to store ARM application programs, system files, and other user data. The specific model information and related parameters of the eMMC Flash are listed in Table 1.5.1.

Position	Reference	Part Number	Capacity	Factory
PS	U8	MTFC8GLVEA-1MWT	8G Byte	Micron

Table 1.5.1-eMMC FLASH Specification

The eMMC Flash is connected to the MIO pins of BANK 500 on the Zynq PS side. In system design, these PS-side MIO pins must be configured to function as eMMC interfaces. The connection of the eMMC Flash in the schematic diagram is shown in Figure 1.5.1.

Figure1.5.1- eMMC Flash in the schematic

Configuration Chip Pin assignment:

Signal Name	Pin Name	Pin Number
EMMC_RST	PS_MIO23	AM27
EMMC_CLK	PS_MIO22	AL27
EMMC_CMD	PS_MIO21	AN28
EMMC_IO0	PS_MIO13	AU26
EMMC_IO1	PS_MIO14	AU27
EMMC_IO2	PS_MIO15	AT27
EMMC_IO3	PS_MIO16	AU28
EMMC_IO4	PS_MIO17	AT28
EMMC_IO5	PS_MIO18	AP28
EMMC_IO6	PS_MIO19	AR27
EMMC_IO7	PS_MIO20	AP27

Table1.5.2-eMMC Flash Pin Configuration

1.6 EEPROM

The ACRF49 SoM includes a built-in EEPROM chip, model AT24CM01, with a capacity of 1 Mbit. It is connected to the PS side via an I2C bus for communication.

EEPROM Pin Assignment:

Signal Name	Pin Name	Pin Number	Remarks
IIC_SCL	PS_MIO24	AL28	I2C Clock Signal
IIC_SDA	PS_MIO25	AM28	I2C Data Signal

Table1.6.1- EEPROM Pin Assignment

1.7 Clock configuration

The ACRF49 SoM provides dual crystal oscillators for system clock generation. The main system clock is supplied by a 33.3333 MHz active crystal oscillator in a 3.2 x 2.5 mm package. In addition, a 32.768 kHz crystal oscillator is used to drive the RFSoC’s internal real-time clock (RTC) circuit. The schematic diagram of the clock circuit design is shown in Figure 1.7.1.

The ACRF49 SoM employs the LMK04828 clock distribution chip to generate and distribute the clocks required by the ADC and DAC modules. The primary reference source is 96 MHz high-stability VCXO. The system supports both a single-ended external reference clock input and a differential SYSREF input, enabling multiple modules to be synchronized in parallel to form large-scale coherent RF channels.

Figure1.7.1- Clock Distribution Connection Schematic

1.8 RF-ADC Interface

The FPGA chip used on the ACRF49 SoM belongs to the Xilinx Zynq UltraScale+ RFSoC Gen3 series, which is the industry’s only single-chip adaptive radio platform. This chip integrates 14-bit RF-ADC channels with a maximum sampling rate of up to 2.5 GSPS, and the corresponding VCM signals are also routed to the board connector for external access.

Figure1.8.1- RF-ADC Interface Schematic

1.9 RF-DAC Interface

The FPGA chip used on the ACRF49 SoM belongs to the Xilinx Zynq UltraScale+ RFSoC Gen3 series, the industry’s only single-chip adaptive radio platform. This chip integrates 14-bit RF-DAC channels with a maximum sampling rate of up to 9.85 GSPS.

Figure1.9.1- RF-DAC Interface Schematic

1.10 High-Speed Board-to-Board Connector

The ACRF49 SoM provides three high-speed expansion interfaces, which are connected to the carrier board via three 400-pin board-to-board connectors (J1, J2, and J3). These connectors use Samtec’s ASP_230332-01 series devices with a 0.635 mm pitch and a mating height of 5 mm, supporting data rates of up to 32 Gbps per channel.

1.11 Power Supply

The ACRF49 SoM is powered by a 12 V DC supply, which is delivered to the SoM through the carrier board via board-to-board connectors. The 12 V system power is converted into multiple voltage rails by high-efficiency step-down (buck) regulators to supply the FPGA and other onboard circuits. The power supplies for the ADC and DAC sections are generated by low-noise linear LDO regulators, providing excellent power supply rejection ratio (PSRR) to ensure high signal integrity and stable performance. The corresponding voltage levels of the SoM expansion I/O BANK interfaces are illustrated in Table 1.11.1.

BANK	Level (V)	Remarks
BANK64	Provided from baseboard, 1.8V	HP BANK
BANK65	Provided from baseboard, 1.8V	HP BANK
BANK66	Provided from baseboard, 1.8V	HP BANK
BANK67	Fixed at 1.2V	DDR4 signals
BANK68	Fixed at 1.2V	DDR4 signals
BANK69	Fixed at 1.2V	DDR4 Signal
BANK84	1.8V Fixed	LMK04828 Configuration Signal and Output
BANK87	Provided from Baseboard, 3.3V	HD BANK
BANK88	Provided from Baseboard, 3.3V	HD BANK
BANK89	Provided from Baseboard, 3.3V	HD BANK
BANK128	MGTY	FMC+ Signal
BANK129	MGTY	FMC+ Signal
BANK130	MGTY	QSFP28 Signal
BANK131	MGTY	QSFP28 Signal
BANK500	1.8V Fixed	QSPI and EMMC Signal
BANK501	Provided from Baseboard	MIO BANK supports 1.8V, 2.5V, and 3.3V at ±5%
BANK502	Provided from Baseboard	MIO BANK supports 1.8V, 2.5V, and 3.3V at ±5%
BANK503	Provided from Baseboard	MIO BANK supports 1.8V, 2.5V, and 3.3V at ±5%
BANK505	PS_MGTR	All high-speed signal pins and clock signals are routed out to the connector

Table 1.11.1- Voltage levels

The power design block diagram of the SoM is shown below:

Figure1.11.1- Power Design Block Diagram

1.12 Structure Diagram

Figure1.12.1- Front View of ACRF49 SoM

Appendix: List of Abbreviations

Abbreviation	Full English Name	Description
PS	Processor System	The processing subsystem in an SoC, typically including CPU cores, memory controllers, and peripheral interfaces for running software and operating systems.
PL	Programmable Logic	User-configurable FPGA logic resources used to implement custom digital circuits, interface controllers, and hardware acceleration functions.
SOC	System on Chip	An integrated circuit that combines processors, memory controllers, peripheral interfaces, and other system functions on a single chip.
DDR3	Double Data Rate 3 SDRAM	A third-generation synchronous dynamic memory technology that transfers data on both edges of the clock signal and is commonly used as system memory.
eMMC	Embedded Multi Media Card	An embedded non-volatile storage device that integrates NAND Flash memory and a storage controller in a single package.
QSPI	Quad Serial Peripheral Interface	A high-speed serial interface that uses four data lines and is commonly used to connect NOR Flash devices for boot or configuration storage.
GTP	Gigabit Transceiver	A high-speed serial transceiver integrated in an FPGA for transmitting and receiving data at multi-gigabit rates.
UART	Universal Asynchronous Receiver/Transmitter	An asynchronous serial communication interface that transmits and receives data through TX and RX signal lines.
HDMI	High-Definition Multimedia Interface	A digital multimedia interface used to transmit high-definition video and audio signals between source and display devices.
PCIe	Peripheral Component Interconnect Express	A high-speed serial expansion bus standard used for communication between processors and devices such as FPGAs, GPUs, and SSDs.
USB	Universal Serial Bus	A standard serial interface used for data communication, peripheral connection, and power delivery between electronic devices.
JTAG	Joint Test Action Group	A standardized interface used for device testing, boundary scan, FPGA programming, and processor or system debugging.
SFP	Small Form-factor Pluggable	A compact, hot-pluggable transceiver interface used for optical or electrical network communication.
MIO	Multiplexed I/O	Multiplexed processor I/O pins in an SoC that can be configured for functions such as UART, I2C, SPI, or GPIO.
GPHY	Gigabit Ethernet PHY	A Gigabit Ethernet physical-layer transceiver that converts digital Ethernet data into electrical signals for transmission over a physical network medium.
I2C	Inter-Integrated Circuit	A two-wire serial communication bus using SDA and SCL lines, commonly used to connect sensors, EEPROMs, and peripheral devices.
RGMII	Reduced Gigabit Media Independent Interface	A reduced-pin-count interface between an Ethernet MAC and PHY that supports 10, 100, and 1000 Mbps Ethernet communication.
RMII	Reduced Media Independent Interface	A reduced-pin-count interface between an Ethernet MAC and PHY, mainly used for 10 and 100 Mbps Ethernet communication.
LED	Light Emitting Diode	A semiconductor device that emits light when electrically driven and is commonly used for power, status, and fault indication.
LVDS	Low-Voltage Differential Signaling	A high-speed differential signaling standard that provides low power consumption, low noise, and strong resistance to electromagnetic interference.

Contact information

Alinx Electronic Limited

Company Website: www.en.alinx.com

Service Hotline: +86 21 67676997

Technical Support:technical@alinx.com