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AXU2CGB-I User Manual
Alinx Electronic Limited
Company Website: www.en.alinx.com
Service Hotline: +86 21 67676997
Technical Support: technical@alinx.com
Document Information
| Item | Content |
| Document Name | User Manual |
| Product Model | AXU2CGB-I |
| Document Version | V1.0 |
| Prepared By | Alinx Electronic Limited |
| Release Date | 2026.11.11 |
Version Control
| Version | Date | Chapter | Revision Summary |
| V1.0 | 2026.11.11 | All | Initial release |
Alinx Electronic Limited has officially released the 2025 version of its development board (model: AXU2CGB-I) built on the XILINX Zynq UltraScale+ MPSoCs development platform. This user manual has been prepared to help you quickly get to know the platform.
This MPSoCs development platform adopts a SoM(System-on-Module) plus carrier board architecture, which makes it easy for users to develop the SoM a second time. The SoM is based on the XILINX Zynq UltraScale+ CG device ZU2CG, which integrates a dual-core ARM Cortex-A53 and FPGA programmable logic in a single chip by means of Processing System (PS) + Programmable Logic (PL) technology. In addition, the PS side of the SoM carries four high-speed DDR4 SDRAM chips with a total capacity of 4GB, one 32GB eMMC storage chip and one 256Mbit QSPI FLASH chip. An additional 1GB DDR4 chip is mounted on the PL side as dedicated storage for the logic section.
On the carrier board we have extended a rich set of peripheral interfaces for users, such as one M.2 interface, one DP interface, four USB3.0 interfaces, two Gigabit Ethernet interfaces, two UART serial interfaces, one Micro SD card slot, two 40-pin expansion ports, two CAN bus interfaces, two RS485 interfaces and one MIPI camera interface. These interfaces meet the requirements of high-speed data exchange, data storage, video transmission and processing, deep learning, artificial intelligence and industrial control, making this a professional-grade ZYNQ development platform. It makes high-speed data transmission and exchange possible, and supports both early verification and later deployment of data processing applications. This product is well suited to students, engineers and other groups engaged in MPSoCs development.
Chapter 1 Development Board Overview
The overall structure of the development board follows our consistent SoM plus carrier board design. The SoM and the carrier board are connected through high-speed board-to-board connectors.
The SoM (ACU2CG-I, the same below) consists of one XCZU2CG, five DDR4 chips, one eMMC FLASH and one QSPI FLASH, forming the minimum system. The XCZU2CG is a member of the Xilinx Zynq UltraScale+ MPSoCs CG series, with the specific part number XCZU2CG-2SFVC784I, and is divided into the Processor System (PS) part and the Programmable Logic (PL) part. On the PS side, four DDR4 chips (4GB in total), one 32GB eMMC FLASH and one 256Mbit QSPI FLASH are attached. The eMMC is used to store the operating system, the file system and user data, while the QSPI FLASH is used to store the boot image. On the PL side, one additional 1GB DDR4 chip is attached as dedicated storage for the logic part.
The carrier board extends a rich set of peripheral interfaces for the SoM, including one PCIe x1 M.2 interface, one Mini DP output interface, four USB3.0 interfaces, two Gigabit Ethernet interfaces, two USB UART interfaces, one Micro SD card slot, two 40-pin expansion ports, two CAN bus interfaces, two RS485 interfaces, one MIPI camera interface and one JTAG debugging port. It also carries an RTC real-time clock, an EEPROM, a temperature sensor, push buttons and LED indicators. The figure below shows the structure of the whole development system:
This diagram shows the interfaces and functions provided by the development platform.
ACU2CG-I SoM: composed of XCZU2CG + 4GB DDR4 (PS) + 32GB eMMC FLASH + 256Mbit QSPI FLASH, plus three clock sources: a single-ended 33.3333MHz oscillator for the PS system, a differential 200MHz oscillator as the reference clock for the PL logic DDR, and a 32.768kHz crystal for the RTC real-time clock.
M.2 interface: one standard PCIe x1 M.2 interface, used to connect an M.2 SSD, with a communication speed of up to 5Gbps.
DP output interface: one standard Mini DisplayPort (mini DP) output interface for video image display, supporting up to 4K@30Hz or 1080P@60Hz output.
USB3.0 interface: four USB3.0 HOST interfaces with Type A connectors, used to connect external USB peripherals such as a mouse, keyboard or USB flash drive.
Gigabit Ethernet interface: two 10/100/1000 Mbps Ethernet RJ45 interfaces, one on the PS side and one on the PL side, used to exchange Ethernet data with a computer or other network devices.
USB UART interface: two interfaces, one on the PS side and one on the PL side, used to communicate with a computer for convenient debugging. The serial chip is the Silicon Labs CP2102GM USB-UART chip and the USB connector is a MINI USB connector.
Micro SD card slot: one Micro SD card slot, used to store the operating system image and the file system.
40-pin expansion port: two 40-pin expansion ports with 2.54mm pitch, to which various ALINX modules can be attached (dual camera, TFT LCD screen, high-speed AD module, etc.). Each expansion port provides one 5V power supply, two 3.3V power supplies, three grounds and 34 IO pins.
CAN communication interface: two CAN bus interfaces using the TI SN65HVD232 chip, with 4-pin green terminal blocks.
RS485 communication interface: two RS485 interfaces using the MAXIM MAX3485 chip, with 6-pin green terminal blocks.
MIPI interface: two-lane MIPI camera input interface, used to connect a MIPI camera module (AN5641).
JTAG debugging port: one standard 10-pin 2.54mm JTAG port, used to download and debug FPGA programs. Users can debug and download the ZU2CG system through a Xilinx downloader.
Temperature sensor: one on-board temperature sensor chip LM75, used to measure the ambient temperature around the board.
EEPROM: one I2C EEPROM 24LC04;
RTC real-time clock: one built-in RTC real-time clock;
LED: five light-emitting diodes, two on the SoM and three on the carrier board. The SoM has one power indicator and one DONE configuration indicator; the carrier board has one power indicator, one PS control indicator and one PL control indicator.
Push buttons: three push buttons, one reset button and two user buttons.
Chapter 2 ACU2CG-I SoM
2.1 Introduction
The ACU2CG-I SoM (the SoM model, the same below) is based on the Xilinx Zynq UltraScale+ MPSoCs CG series, with the specific part number XCZU2CG-2SFVC784I.
This SoM carries five Nanya DDR4 chips NT5AD512M16C4-JRI. Four DDR4 chips are attached on the PS side, forming a 64-bit data bus with 4GB in total, while one chip is attached on the PL side with a 16-bit data bus and 1GB capacity. The PS-side DDR4 SDRAM runs at up to 1200MHz (2400Mbps data rate), and the PL-side DDR4 SDRAM runs at up to 1066MHz (2132Mbps data rate). The SoM also integrates one 256Mbit QSPI FLASH for storing the boot image and one 32GB eMMC FLASH for storing system files.
To connect with the carrier board, the four board-to-board connectors on this SoM bring out the PS-side USB2.0 interface, Gigabit Ethernet interface, Micro SD card slot and the remaining MIO pins, as well as four pairs of PS MGT high-speed transceiver interfaces and almost all PL-side IO (HP I/O: 96, HD I/O: 84). The routing between the XCZU2CG and the connectors is length-matched and differential-pair routed, and the SoM measures only 80*60 (mm), which makes it very suitable for secondary development.
Figure 2.1.1 - ACU2CG-I SoM Front View
2.2 Zynq Chip
The PS system of the XCZU2CG-2SFVC784I integrates two ARM Cortex-A53 processors running at up to 1.2GHz with level-2 cache support, and also contains two Cortex-R5 processors running at up to 500MHz.
The XCZU2CG supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L and LPDDR3 memory chips, and provides rich high-speed interfaces on the PS side such as PCIe Gen2, USB3.0, SATA 3.1 and DisplayPort. It also supports USB2.0, Gigabit Ethernet, SD/SDIO, I2C, CAN, UART and GPIO interfaces. The PL side contains abundant programmable logic cells, DSP slices and internal RAM. The overall block diagram of the XCZU2CG is shown below:
Figure 2.2.1 - Block Diagram of the ZYNQ ZU2CG Chip
The main parameters of the PS system are as follows:
Dual-core ARM Cortex-A53 processors running at up to 1.2GHz, with 32KB level-1 instruction and data cache per CPU and 1MB level-2 cache shared by both CPUs.
Dual-core ARM Cortex-R5 processors running at up to 500MHz, with 32KB level-1 instruction and data cache per CPU and 128K tightly coupled memory.
External memory interface, supporting 32/64-bit DDR4/3/3L and LPDDR4/3 interfaces.
Static memory interface, supporting NAND and 2x Quad-SPI FLASH.
High-speed connectivity interfaces, supporting PCIe Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort and 4x Tri-mode Gigabit Ethernet.
General connectivity interfaces: 2x USB2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI and 4x 32b GPIO.
Power management: supports the Full/Low/PL/Battery power domain partitioning.
Encryption algorithms: supports RSA, AES and SHA.
System monitoring: 10-bit 1Mbps AD sampling for temperature and voltage monitoring.
The main parameters of the PL logic are as follows:
Logic Cells: 103K;
Flip-flops: 94K;
Look-up tables (LUTs): 47K;
Block RAM: 5.3Mbit;
Clock management tiles (CMTs): 3
Multipliers 18x25MACCs: 240
The speed grade of the XCZU2CG-2SFVC784I is -2, industrial grade, in the SFVC784 package.
2.3 DDR4 DRAM
The ACU2CG-I SoM is equipped with five DDR4 chips, model Nanya NT5AD512M16C4-JRI (compatible with MT40A256M16GE-083E); four chips on the PS side form a 64-bit bus with 4GB in total, and one chip on the PL side provides a 16-bit bus with 1GB, giving 5GB in total. The DDR4 SDRAM runs at up to 1200MHz (2400Mbps data rate), and the four PS-side DDR4 chips are connected directly to the memory interface of BANK504. The detailed DDR4 SDRAM configuration is shown in Table 2.3.1.
| Designator | Chip Model | Capacity | Manufacturer |
| U12,U14,U15,U16,U17 | NT5AD512M16C4-JRI | 512M x 16bit | Nanya |
Table 2.3.1 - DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of signal integrity. During circuit and PCB design we have fully taken into account matching/termination resistors, trace impedance control and trace length matching, so as to guarantee high-speed and stable DDR4 operation. The hardware connection of the PS-side DDR4 is shown in Figure 2.3.1, and that of the PL-side DDR4 (16-bit, 1GB) is shown in Figure 2.3.2:
Figure 2.3.1 - Schematic of the PS-Side DDR4 DRAM
Figure 2.3.2 - Schematic of the PL-Side DDR4 DRAM
PS-side DDR4 SDRAM pin assignment:
| Signal Name | Pin Name | Pin Number |
| PS_DDR4_DQS0_P | PS_DDR_DQS_P0_504 | AF21 |
| PS_DDR4_DQS0_N | PS_DDR_DQS_N0_504 | AG21 |
| PS_DDR4_DQS1_P | PS_DDR_DQS_P1_504 | AF23 |
| PS_DDR4_DQS1_N | PS_DDR_DQS_N1_504 | AG23 |
| PS_DDR4_DQS2_P | PS_DDR_DQS_P2_504 | AF25 |
| PS_DDR4_DQS2_N | PS_DDR_DQS_N2_504 | AF26 |
| PS_DDR4_DQS3_P | PS_DDR_DQS_P3_504 | AE27 |
| PS_DDR4_DQS3_N | PS_DDR_DQS_N3_504 | AF27 |
| PS_DDR4_DQS4_P | PS_DDR_DQS_P4_504 | N23 |
| PS_DDR4_DQS4_N | PS_DDR_DQS_N4_504 | M23 |
| PS_DDR4_DQS5_P | PS_DDR_DQS_P5_504 | L23 |
| PS_DDR4_DQS5_N | PS_DDR_DQS_N5_504 | K23 |
| PS_DDR4_DQS6_P | PS_DDR_DQS_P6_504 | N26 |
| PS_DDR4_DQS6_N | PS_DDR_DQS_N6_504 | N27 |
| PS_DDR4_DQS7_P | PS_DDR_DQS_P7_504 | J26 |
| PS_DDR4_DQS7_N | PS_DDR_DQS_N7_504 | J27 |
| PS_DDR4_DQ0 | PS_DDR_DQ0_504 | AD21 |
| PS_DDR4_DQ1 | PS_DDR_DQ1_504 | AE20 |
| PS_DDR4_DQ2 | PS_DDR_DQ2_504 | AD20 |
| PS_DDR4_DQ3 | PS_DDR_DQ3_504 | AF20 |
| PS_DDR4_DQ4 | PS_DDR_DQ4_504 | AH21 |
| PS_DDR4_DQ5 | PS_DDR_DQ5_504 | AH20 |
| PS_DDR4_DQ6 | PS_DDR_DQ6_504 | AH19 |
| PS_DDR4_DQ7 | PS_DDR_DQ7_504 | AG19 |
| PS_DDR4_DQ8 | PS_DDR_DQ8_504 | AF22 |
| PS_DDR4_DQ9 | PS_DDR_DQ9_504 | AH22 |
| PS_DDR4_DQ10 | PS_DDR_DQ10_504 | AE22 |
| PS_DDR4_DQ11 | PS_DDR_DQ11_504 | AD22 |
| PS_DDR4_DQ12 | PS_DDR_DQ12_504 | AH23 |
| PS_DDR4_DQ13 | PS_DDR_DQ13_504 | AH24 |
| PS_DDR4_DQ14 | PS_DDR_DQ14_504 | AE24 |
| PS_DDR4_DQ15 | PS_DDR_DQ15_504 | AG24 |
| PS_DDR4_DQ16 | PS_DDR_DQ16_504 | AC26 |
| PS_DDR4_DQ17 | PS_DDR_DQ17_504 | AD26 |
| PS_DDR4_DQ18 | PS_DDR_DQ18_504 | AD25 |
| PS_DDR4_DQ19 | PS_DDR_DQ19_504 | AD24 |
| PS_DDR4_DQ20 | PS_DDR_DQ20_504 | AG26 |
| PS_DDR4_DQ21 | PS_DDR_DQ21_504 | AH25 |
| PS_DDR4_DQ22 | PS_DDR_DQ22_504 | AH26 |
| PS_DDR4_DQ23 | PS_DDR_DQ23_504 | AG25 |
| PS_DDR4_DQ24 | PS_DDR_DQ24_504 | AH27 |
| PS_DDR4_DQ25 | PS_DDR_DQ25_504 | AH28 |
| PS_DDR4_DQ26 | PS_DDR_DQ26_504 | AF28 |
| PS_DDR4_DQ27 | PS_DDR_DQ27_504 | AG28 |
| PS_DDR4_DQ28 | PS_DDR_DQ28_504 | AC27 |
| PS_DDR4_DQ29 | PS_DDR_DQ29_504 | AD27 |
| PS_DDR4_DQ30 | PS_DDR_DQ30_504 | AD28 |
| PS_DDR4_DQ31 | PS_DDR_DQ31_504 | AC28 |
| PS_DDR4_DQ32 | PS_DDR_DQ32_504 | T22 |
| PS_DDR4_DQ33 | PS_DDR_DQ33_504 | R22 |
| PS_DDR4_DQ34 | PS_DDR_DQ34_504 | P22 |
| PS_DDR4_DQ35 | PS_DDR_DQ35_504 | N22 |
| PS_DDR4_DQ36 | PS_DDR_DQ36_504 | T23 |
| PS_DDR4_DQ37 | PS_DDR_DQ37_504 | P24 |
| PS_DDR4_DQ38 | PS_DDR_DQ38_504 | R24 |
| PS_DDR4_DQ39 | PS_DDR_DQ39_504 | N24 |
| PS_DDR4_DQ40 | PS_DDR_DQ40_504 | H24 |
| PS_DDR4_DQ41 | PS_DDR_DQ41_504 | J24 |
| PS_DDR4_DQ42 | PS_DDR_DQ42_504 | M24 |
| PS_DDR4_DQ43 | PS_DDR_DQ43_504 | K24 |
| PS_DDR4_DQ44 | PS_DDR_DQ44_504 | J22 |
| PS_DDR4_DQ45 | PS_DDR_DQ45_504 | H22 |
| PS_DDR4_DQ46 | PS_DDR_DQ46_504 | K22 |
| PS_DDR4_DQ47 | PS_DDR_DQ47_504 | L22 |
| PS_DDR4_DQ48 | PS_DDR_DQ48_504 | M25 |
| PS_DDR4_DQ49 | PS_DDR_DQ49_504 | M26 |
| PS_DDR4_DQ50 | PS_DDR_DQ50_504 | L25 |
| PS_DDR4_DQ51 | PS_DDR_DQ51_504 | L26 |
| PS_DDR4_DQ52 | PS_DDR_DQ52_504 | K28 |
| PS_DDR4_DQ53 | PS_DDR_DQ53_504 | L28 |
| PS_DDR4_DQ54 | PS_DDR_DQ54_504 | M28 |
| PS_DDR4_DQ55 | PS_DDR_DQ55_504 | N28 |
| PS_DDR4_DQ56 | PS_DDR_DQ56_504 | J28 |
| PS_DDR4_DQ57 | PS_DDR_DQ57_504 | K27 |
| PS_DDR4_DQ58 | PS_DDR_DQ58_504 | H28 |
| PS_DDR4_DQ59 | PS_DDR_DQ59_504 | H27 |
| PS_DDR4_DQ60 | PS_DDR_DQ60_504 | G26 |
| PS_DDR4_DQ61 | PS_DDR_DQ61_504 | G25 |
| PS_DDR4_DQ62 | PS_DDR_DQ62_504 | K25 |
| PS_DDR4_DQ63 | PS_DDR_DQ63_504 | J25 |
| PS_DDR4_DM0 | PS_DDR_DM0_504 | AG20 |
| PS_DDR4_DM1 | PS_DDR_DM1_504 | AE23 |
| PS_DDR4_DM2 | PS_DDR_DM2_504 | AE25 |
| PS_DDR4_DM3 | PS_DDR_DM3_504 | AE28 |
| PS_DDR4_DM4 | PS_DDR_DM4_504 | R23 |
| PS_DDR4_DM5 | PS_DDR_DM5_504 | H23 |
| PS_DDR4_DM6 | PS_DDR_DM6_504 | L27 |
| PS_DDR4_DM7 | PS_DDR_DM7_504 | H26 |
| PS_DDR4_A0 | PS_DDR_A0_504 | W28 |
| PS_DDR4_A1 | PS_DDR_A1_504 | Y28 |
| PS_DDR4_A2 | PS_DDR_A2_504 | AB28 |
| PS_DDR4_A3 | PS_DDR_A3_504 | AA28 |
| PS_DDR4_A4 | PS_DDR_A4_504 | Y27 |
| PS_DDR4_A5 | PS_DDR_A5_504 | AA27 |
| PS_DDR4_A6 | PS_DDR_A6_504 | Y22 |
| PS_DDR4_A7 | PS_DDR_A7_504 | AA23 |
| PS_DDR4_A8 | PS_DDR_A8_504 | AA22 |
| PS_DDR4_A9 | PS_DDR_A9_504 | AB23 |
| PS_DDR4_A10 | PS_DDR_A10_504 | AA25 |
| PS_DDR4_A11 | PS_DDR_A11_504 | AA26 |
| PS_DDR4_A12 | PS_DDR_A12_504 | AB25 |
| PS_DDR4_A13 | PS_DDR_A13_504 | AB26 |
| PS_DDR4_WE_B | PS_DDR_A14_504 | AB24 |
| PS_DDR4_CAS_B | PS_DDR_A15_504 | AC24 |
| PS_DDR4_RAS_B | PS_DDR_A16_504 | AC23 |
| PS_DDR4_ACT_B | PS_DDR_ACT_N_504 | Y23 |
| PS_DDR4_ALERT_B | PS_DDR_ALERT_N_504 | U25 |
| PS_DDR4_BA0 | PS_DDR_BA0_504 | V23 |
| PS_DDR4_BA1 | PS_DDR_BA1_504 | W22 |
| PS_DDR4_BG0 | PS_DDR_BG0_504 | W24 |
| PS_DDR4_CS0_B | PS_DDR_CS_N0_504 | W27 |
| PS_DDR4_ODT0 | PS_DDR_ODT0_504 | U28 |
| PS_DDR4_PARITY | PS_DDR_PARITY_504 | V24 |
| PS_DDR4_RESET_B | PS_DDR_RST_N_504 | U23 |
| PS_DDR4_CLK0_P | PS_DDR_CK0_P_504 | W25 |
| PS_DDR4_CLK0_N | PS_DDR_CK0_N_504 | W26 |
| PS_DDR4_CKE0 | PS_DDR_CKE0_504 | V28 |
Table 2.3.2 - DDR4 SDRAM Pin Assignment
2.4 QSPI FLASH
The ACU2CG-I SoM is equipped with one 256Mbit Quad-SPI FLASH chip forming a 4-bit wide data bus. The FLASH model is MT25QU256ABA1EW9 and it uses the 1.8V CMOS voltage standard. Because QSPI FLASH is non-volatile, it can serve as the boot device of the system and store the boot images, which mainly include the FPGA bitstream, the ARM application code and other user data files. The specific model and related parameters of the QSPI FLASH are listed in Table 2.4.1.
| Designator | Chip Type | Capacity | Manufacturer |
| U5 | MT25QU256ABA1EW9 | 256Mbit | Micron |
Table 2.4.1 - QSPI Flash Model and Parameters
The QSPI FLASH is connected to the GPIO pins of BANK500 on the PS side of the Zynq chip. In system design these PS GPIO pins must be configured as the QSPI FLASH interface. Figure 2.4.1 shows the QSPI FLASH in the schematic.
Figure 2.4.1 - QSPI Flash Connection Diagram
Configuration chip pin assignment:
| Signal Name | Pin Name | Pin Number |
| MIO0_QSPI0_SCLK | PS_MIO0_500 | AG15 |
| MIO1_QSPI0_IO1 | PS_MIO1_500 | AG16 |
| MIO2_QSPI0_IO2 | PS_MIO2_500 | AF15 |
| MIO3_QSPI0_IO3 | PS_MIO3_500 | AH15 |
| MIO4_QSPI0_IO0 | PS_MIO4_500 | AH16 |
| MIO5_QSPI0_SS_B | PS_MIO5_500 | AD16 |
Table 2.4.2 - QSPI Flash Pin Assignment
2.5 eMMC FLASH
The ACU2CG-I SoM is equipped with one 32GB eMMC FLASH chip, model MTFC32GBCAQTC-IT (compatible with Micron MTFC8GAKAJCN-4M). It supports the HS-MMC interface of the JEDEC e-MMC V5.0 standard, with 1.8V or 3.3V I/O levels. The data width between the eMMC FLASH and the Zynq is 8 bits. Thanks to its large capacity and non-volatile nature, the eMMC FLASH can serve as the large-capacity storage device of the Zynq system, for example to store ARM applications, system files and other user data files. The specific model and related parameters of the eMMC FLASH are listed in Table 2.5.1.
| Designator | Chip Type | Capacity | Manufacturer |
| U19 | MTFC32GBCAQTC-IT | 32GB | Micron |
Table 2.5.1 - eMMC Flash Model and Parameters
The eMMC FLASH is connected to the GPIO pins of BANK500 on the PS side of the Zynq UltraScale+. In system design these PS GPIO pins must be configured as the eMMC interface. Figure 2.5.1 shows the eMMC FLASH in the schematic.
Figure 2.5.1 - eMMC Flash Connection Diagram
Configuration chip pin assignment:
| Signal Name | Pin Name | Pin Number |
| MMC_DAT0 | PS_MIO13_500 | AH18 |
| MMC_DAT1 | PS_MIO14_500 | AG18 |
| MMC_DAT2 | PS_MIO15_500 | AE18 |
| MMC_DAT3 | PS_MIO16_500 | AF18 |
| MMC_DAT4 | PS_MIO17_500 | AC18 |
| MMC_DAT5 | PS_MIO18_500 | AC19 |
| MMC_DAT6 | PS_MIO19_500 | AE19 |
| MMC_DAT7 | PS_MIO20_500 | AD19 |
| MMC_CMD | PS_MIO21_500 | AC21 |
| MMC_CCLK | PS_MIO22_500 | AB20 |
| MMC_RSTN | PS_MIO23_500 | AB18 |
Table 2.5.2 - eMMC Flash Pin Assignment
2.6 Clock Configuration
The SoM provides reference clocks for the PS system and the PL logic separately, and the PS system has an additional RTC real-time clock, so that the PS system and the PL logic can operate independently. The clock circuit design is shown in Figure 2.6.1:
Figure 2.6.1 - Clock Sources of the SoM
PS System RTC Real-Time Clock
The passive crystal Y2 on the SoM provides a 32.768kHz real-time clock source for the PS system. The crystal is connected to the PS_PADI_503 and PS_PADO_503 pins of BANK503 on the Zynq chip. The clock pin assignment is shown in the table below:
| Signal Name | Pin |
| PS_PADI_503 | N17 |
| PS_PADO_503 | N18 |
Table 2.6.1 - RTC Clock Pin Assignment
PS System Clock Source
The X1 oscillator on the SoM provides a 33.3333MHz clock input for the PS part. The clock input is connected to the PS_REF_CLK_503 pin of BANK503 on the Zynq chip. The clock pin assignment is shown in the table below:
| Signal Name | Pin |
| PS_CLK | R16 |
Table 2.6.2 - PS System Clock Pin Assignment
PL System Clock Source
A differential 200MHz PL system clock source is provided on the board as the reference clock for the DDR4 controller. The oscillator output is connected to the global clock (MRCC) of PL BANK64, and this global clock can be used to drive the DDR4 controller and user logic inside the FPGA. The PL clock pin assignment is shown in the table below:
| Signal Name | Pin |
| PL_CLK0_P | AE5 |
| PL_CLK0_N | AF5 |
Table 2.6.3 - PL System Clock Pin Assignment
2.7 LEDs
The ACU2CG-I SoM has one red power indicator (PWR) and one configuration LED (DONE). The power indicator lights up once the SoM is powered, and the configuration LED lights up once the FPGA is configured. The hardware connection of the LEDs is shown in Figure 2.7.1:
Figure 2.7.1 - LED Hardware Connection on the SoM
2.8 Power Supply
The supply voltage of the ACU2CG-I SoM is +12V, provided by the carrier board through the board-to-board connectors. On the SoM, a PMIC chip TPS6508641 generates all the supplies required by the XCZU2CG. For the TPS6508641 power design please refer to the power chip datasheet; the design block diagram is as follows:
Figure 2.8.1 - Power Design Block Diagram
In addition, the VCCIO supplies of BANK65 and BANK66 of the XCZU2CG are provided by the carrier board for easy modification by the user, but the supply must not exceed 1.8V.
2.9 Structure Diagram
Figure 2.9.1 - Mechanical Dimensions
2.10 Connector Pin Definition
The SoM brings out four high-speed expansion ports and connects to the carrier board through four 120-pin board-to-board connectors (J29 to J32). The connectors are Panasonic AXK5A2137YG, and the mating connectors on the carrier board are AXK6A2337YG. J29 carries the IO of BANK65 and BANK66; J30 carries the IO of BANK45, BANK46 and BANK66 together with the transceiver signals of BANK505 MGT; J31 carries the IO of BANK43 and BANK44; J32 carries the PS MIO, VCCO_65, VCCO_66 and the +12V supply.
The IO level standard of BANK43 to BANK46 is 3.3V. The level standard of BANK65 and BANK66 is determined by the VCCO_65 and VCCO_66 supplies of the carrier board and must not exceed +1.8V. The MIO level standard is also 1.8V.
Pin assignment of the J29 connector
| J29 Pin | Signal Name | Pin Number | J29 Pin | Signal Name | Pin Number |
| 1 | B65_L2_N | V9 | 2 | B65_L22_P | K8 |
| 3 | B65_L2_P | U9 | 4 | B65_L22_N | K7 |
| 5 | GND | - | 6 | GND | - |
| 7 | B65_L4_N | T8 | 8 | B65_L20_P | J6 |
| 9 | B65_L4_P | R8 | 10 | B65_L20_N | H6 |
| 11 | GND | - | 12 | GND | - |
| 13 | B65_L1_N | Y8 | 14 | B65_L6_N | T6 |
| 15 | B65_L1_P | W8 | 16 | B65_L6_P | R6 |
| 17 | GND | - | 18 | GND | - |
| 19 | B65_L7_P | L1 | 20 | B65_L17_P | N9 |
| 21 | B65_L7_N | K1 | 22 | B65_L17_N | N8 |
| 23 | GND | - | 24 | GND | - |
| 25 | B65_L15_P | N7 | 26 | B65_L9_P | K2 |
| 27 | B65_L15_N | N6 | 28 | B65_L9_N | J2 |
| 29 | GND | - | 30 | GND | - |
| 31 | B65_L16_P | P7 | 32 | B65_L3_N | V8 |
| 33 | B65_L16_N | P6 | 34 | B65_L3_P | U8 |
| 35 | GND | - | 36 | GND | - |
| 37 | B65_L14_P | M6 | 38 | B65_L19_P | J5 |
| 39 | B65_L14_N | L5 | 40 | B65_L19_N | J4 |
| 41 | GND | - | 42 | GND | - |
| 43 | B65_L5_N | T7 | 44 | B65_L18_P | M8 |
| 45 | B65_L5_P | R7 | 46 | B65_L18_N | L8 |
| 47 | GND | - | 48 | GND | - |
| 49 | B65_L11_N | K3 | 50 | B65_L8_P | J1 |
| 51 | B65_L11_P | K4 | 52 | B65_L8_N | H1 |
| 53 | GND | - | 54 | GND | - |
| 55 | B65_L10_N | H3 | 56 | B65_L24_N | H8 |
| 57 | B65_L10_P | H4 | 58 | B65_L24_P | H9 |
| 59 | GND | - | 60 | GND | - |
| 61 | B66_L3_P | F2 | 62 | B65_L12_P | L3 |
| 63 | B66_L3_N | E2 | 64 | B65_L12_N | L2 |
| 65 | GND | - | 66 | GND | - |
| 67 | B66_L1_P | G1 | 68 | B65_L13_N | L6 |
| 69 | B66_L1_N | F1 | 70 | B65_L13_P | L7 |
| 71 | GND | - | 72 | GND | - |
| 73 | B66_L6_P | G5 | 74 | B65_L21_P | J7 |
| 75 | B66_L6_N | F5 | 76 | B65_L21_N | H7 |
| 77 | GND | - | 78 | GND | - |
| 79 | B66_L16_P | G8 | 80 | B65_L23_P | K9 |
| 81 | B66_L16_N | F7 | 82 | B65_L23_N | J9 |
| 83 | GND | - | 84 | GND | - |
| 85 | B66_L15_P | G6 | 86 | B66_L5_N | E3 |
| 87 | B66_L15_N | F6 | 88 | B66_L5_P | E4 |
| 89 | GND | - | 90 | GND | - |
| 91 | B66_L4_P | G3 | 92 | B66_L2_P | E1 |
| 93 | B66_L4_N | F3 | 94 | B66_L2_N | D1 |
| 95 | GND | - | 96 | GND | - |
| 97 | B66_L11_P | D4 | 98 | B66_L20_P | C6 |
| 99 | B66_L11_N | C4 | 100 | B66_L20_N | B6 |
| 101 | GND | - | 102 | GND | - |
| 103 | B66_L12_P | C3 | 104 | B66_L7_P | C1 |
| 105 | B66_L12_N | C2 | 106 | B66_L7_N | B1 |
| 107 | GND | - | 108 | GND | - |
| 109 | B66_L13_N | D6 | 110 | B66_L10_P | B4 |
| 111 | B66_L13_P | D7 | 112 | B66_L10_N | A4 |
| 113 | GND | - | 114 | GND | - |
| 115 | B66_L8_N | A1 | 116 | B66_L9_P | B3 |
| 117 | B66_L8_P | A2 | 118 | B66_L9_N | A3 |
| 119 | GND | - | 120 | GND | - |
Table 2.10.1 - J29 Connector Pin Assignment
Pin assignment of the J30 connector
| J30 Pin | Signal Name | Pin Number | J30 Pin | Signal Name | Pin Number |
| 1 | B66_L14_P | E5 | 2 | FPGA_TDI | R18 |
| 3 | B66_L14_N | D5 | 4 | FPGA_TCK | R19 |
| 5 | GND | - | 6 | GND | - |
| 7 | B66_L22_P | C8 | 8 | FPGA_TDO | T21 |
| 9 | B66_L22_N | B8 | 10 | FPGA_TMS | N21 |
| 11 | GND | - | 12 | GND | - |
| 13 | B66_L19_N | A5 | 14 | B66_L21_N | A6 |
| 15 | B66_L19_P | B5 | 16 | B66_L21_P | A7 |
| 17 | GND | - | 18 | GND | - |
| 19 | B66_L24_P | C9 | 20 | B66_L17_P | F8 |
| 21 | B66_L24_N | B9 | 22 | B66_L17_N | E8 |
| 23 | GND | - | 24 | GND | - |
| 25 | B66_L23_N | A8 | 26 | B45_L9_P | C11 |
| 27 | B66_L23_P | A9 | 28 | B45_L9_N | B10 |
| 29 | GND | - | 30 | GND | - |
| 31 | B45_L5_N | F10 | 32 | B45_L10_P | B11 |
| 33 | B45_L5_P | G11 | 34 | B45_L10_N | A10 |
| 35 | GND | - | 36 | GND | - |
| 37 | B66_L18_N | D9 | 38 | B45_L12_P | D12 |
| 39 | B66_L18_P | E9 | 40 | B45_L12_N | C12 |
| 41 | GND | - | 42 | GND | - |
| 43 | B45_L4_N | H12 | 44 | B45_L11_P | A12 |
| 45 | B45_L4_P | J12 | 46 | B45_L11_N | A11 |
| 47 | GND | - | 48 | GND | - |
| 49 | B46_L11_P | K14 | 50 | B45_L6_N | F11 |
| 51 | B46_L11_N | J14 | 52 | B45_L6_P | F12 |
| 53 | GND | - | 54 | GND | - |
| 55 | B46_L10_N | H13 | 56 | B46_L6_N | E13 |
| 57 | B46_L10_P | H14 | 58 | B46_L6_P | E14 |
| 59 | GND | - | 60 | GND | - |
| 61 | B46_L7_N | F13 | 62 | B46_L3_N | A13 |
| 63 | B46_L7_P | G13 | 64 | B46_L3_P | B13 |
| 65 | GND | - | 66 | GND | - |
| 67 | B46_L9_N | G14 | 68 | B46_L2_N | A14 |
| 69 | B46_L9_P | G15 | 70 | B46_L2_P | B14 |
| 71 | GND | - | 72 | GND | - |
| 73 | B46_L5_N | D14 | 74 | B46_L4_N | C13 |
| 79 | B46_L5_P | D15 | 76 | B46_L4_P | C14 |
| 77 | GND | - | 78 | GND | - |
| 79 | B46_L1_P | B15 | 80 | B46_L12_P | L14 |
| 81 | B46_L1_N | A15 | 82 | B46_L12_N | L13 |
| 83 | GND | - | 84 | GND | - |
| 85 | 505_CLK2_P | C21 | 86 | 505_CLK1_P | E21 |
| 87 | 505_CLK2_N | C22 | 88 | 505_CLK1_N | E22 |
| 89 | GND | - | 90 | GND | - |
| 91 | 505_CLK0_P | F23 | 92 | 505_CLK3_P | A21 |
| 93 | 505_CLK0_N | F24 | 94 | 505_CLK3_N | A22 |
| 95 | GND | - | 96 | GND | - |
| 97 | 505_TX0_P | E25 | 98 | 505_TX3_P | B23 |
| 99 | 505_TX0_N | E26 | 100 | 505_TX3_N | B24 |
| 101 | GND | - | 102 | GND | - |
| 103 | 505_RX0_P | F27 | 104 | 505_RX3_P | A25 |
| 105 | 505_RX0_N | F28 | 106 | 505_RX3_N | A26 |
| 107 | GND | - | 108 | GND | - |
| 109 | 505_TX1_P | D23 | 110 | 505_TX2_P | C25 |
| 111 | 505_TX1_N | D24 | 112 | 505_TX2_N | C26 |
| 113 | GND | - | 114 | GND | - |
| 115 | 505_RX1_P | D27 | 116 | 505_RX2_P | B27 |
| 117 | 505_RX1_N | D28 | 118 | 505_RX2_N | B28 |
| 119 | GND | - | 120 | GND | - |
Table 2.10.2 - J30 Connector Pin Assignment
Pin assignment of the J31 connector
| J31 Pin | Signal Name | Pin Number | J31 Pin | Signal Name | Pin Number |
| 1 | B44_L10_P | Y14 | 2 | B44_L7_P | AA13 |
| 3 | B44_L10_N | Y13 | 4 | B44_L7_N | AB13 |
| 5 | GND | - | 6 | GND | - |
| 7 | B44_L6_P | AC14 | 8 | B43_L6_P | AC12 |
| 9 | B44_L6_N | AC13 | 10 | B43_L6_N | AD12 |
| 11 | GND | - | 12 | GND | - |
| 13 | B44_L5_P | AD15 | 14 | B43_L7_P | AD11 |
| 15 | B44_L5_N | AD14 | 16 | B43_L7_N | AD10 |
| 17 | GND | - | 18 | GND | - |
| 19 | B44_L1_P | AE15 | 20 | B43_L8_N | AC11 |
| 21 | B44_L1_N | AE14 | 22 | B43_L8_P | AB11 |
| 23 | GND | - | 24 | GND | - |
| 25 | B44_L12_P | Y12 | 26 | B44_L2_P | AG14 |
| 27 | B44_L12_N | AA12 | 28 | B44_L2_N | AH14 |
| 29 | GND | - | 30 | GND | - |
| 31 | B44_L3_P | AG13 | 32 | - | - |
| 33 | B44_L3_N | AH13 | 34 | - | - |
| 35 | GND | - | 36 | GND | - |
| 37 | B43_L12_N | AB9 | 38 | B43_L9_P | AA11 |
| 39 | B43_L12_P | AB10 | 40 | B43_L9_N | AA10 |
| 41 | GND | - | 42 | GND | - |
| 43 | B43_L10_N | Y10 | 44 | B43_L3_P | AH12 |
| 45 | B43_L10_P | W10 | 46 | B43_L3_N | AH11 |
| 47 | GND | - | 48 | GND | - |
| 49 | B44_L11_N | W11 | 50 | B43_L1_N | AH10 |
| 51 | B44_L11_P | W12 | 52 | B43_L1_P | AG10 |
| 53 | GND | - | 54 | GND | - |
| 55 | B44_L9_N | W13 | 56 | B44_L4_P | AE13 |
| 57 | B44_L9_P | W14 | 58 | B44_L4_N | AF13 |
| 59 | GND | - | 60 | GND | - |
| 61 | B44_L8_P | AB15 | 62 | B43_L5_P | AE12 |
| 63 | B44_L8_N | AB14 | 64 | B43_L5_N | AF12 |
| 65 | GND | - | 66 | GND | - |
| 67 | B43_L2_N | AG11 | 68 | B43_L4_P | AE10 |
| 69 | B43_L2_P | AF11 | 70 | B43_L4_N | AF10 |
| 71 | GND | - | 72 | GND | - |
| 73 | VBAT_IN | - | 74 | B43_L11_P | Y9 |
| 75 | MR | - | 76 | B43_L11_N | AA8 |
| 77 | GND | - | 78 | GND | - |
| 79 | - | - | 80 | PS_POR_B | P16 |
| 81 | - | - | 82 | - | - |
| 83 | GND | - | 84 | GND | - |
| 86 | - | - | 86 | - | - |
| 87 | - | 88 | - | - | |
| 89 | GND | - | 90 | GND | - |
| 91 | 224_CLK0_P | Y6 | 92 | 224_CLK1_P | V6 |
| 93 | 224_CLK0_N | Y5 | 94 | 224_CLK1_N | V5 |
| 95 | GND | - | 96 | GND | - |
| 97 | 224_TX3_N | N3 | 98 | 224_RX3_N | P1 |
| 99 | 224_TX3_P | N4 | 100 | 224_RX3_P | P2 |
| 101 | GND | - | 102 | GND | |
| 103 | 224_TX2_N | R3 | 104 | 224_RX2_N | T1 |
| 105 | 224_TX2_P | R4 | 106 | 224_RX2_P | T2 |
| 107 | GND | 108 | GND | ||
| 109 | 224_TX1_N | U3 | 110 | 224_RX1_N | V1 |
| 111 | 224_TX1_P | U4 | 112 | 224_RX1_P | V2 |
| 113 | GND | - | 114 | GND | - |
| 115 | 224_TX0_N | W3 | 116 | 224_RX0_N | Y1 |
| 117 | 224_TX0_P | W4 | 118 | 224_RX0_P | Y2 |
| 119 | GND | - | 120 | GND | - |
Table 2.10.3 - J31 Connector Pin Assignment
Pin assignment of the J32 connector
| J32 Pin | Signal Name | Pin Number | J32 Pin | Signal Name | Pin Number |
| 1 | PS_MIO35 | H17 | 2 | PS_MIO30 | F16 |
| 3 | PS_MIO29 | G16 | 4 | PS_MIO31 | H16 |
| 5 | GND | - | - | GND | - |
| 7 | - | - | 8 | PS_MIO58 | F18 |
| 9 | - | - | 10 | PS_MIO53 | D16 |
| 11 | GND | - | 12 | GND | - |
| 13 | PS_MODE0 | P19 | 14 | PS_MIO52 | G18 |
| 15 | PS_MODE1 | P20 | 16 | PS_MIO55 | B16 |
| 17 | GND | - | 18 | GND | - |
| 19 | PS_MODE2 | R20 | 20 | PS_MIO56 | C16 |
| 21 | PS_MODE3 | T20 | 22 | PS_MIO57 | A16 |
| 23 | GND | - | 24 | GND | - |
| 25 | PS_MIO36 | K17 | 26 | PS_MIO54 | F17 |
| 27 | PS_MIO37 | J17 | 28 | PS_MIO27 | J15 |
| 29 | GND | - | 30 | GND | - |
| 31 | - | - | 32 | PS_MIO28 | K15 |
| 33 | PS_MIO77 | F20 | 34 | PS_MIO59 | E17 |
| 35 | GND | - | 36 | GND | - |
| 37 | PS_MIO76 | B20 | 38 | PS_MIO60 | C17 |
| 39 | - | - | 40 | PS_MIO61 | D17 |
| 41 | GND | - | 42 | GND | - |
| 43 | PS_MIO39 | H19 | 44 | PS_MIO62 | A17 |
| 45 | PS_MIO38 | H18 | 46 | PS_MIO63 | E18 |
| 47 | GND | - | 48 | GND | - |
| 49 | - | - | 50 | PS_MIO65 | A18 |
| 51 | PS_MIO40 | K18 | 52 | PS_MIO66 | G19 |
| 53 | GND | - | 54 | GND | - |
| 55 | PS_MIO44 | J20 | 56 | PS_MIO67 | B18 |
| 57 | PS_MIO45 | K20 | 58 | PS_MIO68 | C18 |
| 59 | GND | - | 60 | GND | - |
| 61 | PS_MIO47 | H21 | 62 | PS_MIO64 | E19 |
| 63 | PS_MIO48 | J21 | 64 | PS_MIO69 | D19 |
| 65 | GND | - | 66 | GND | - |
| 67 | PS_MIO41 | J19 | 68 | PS_MIO74 | D20 |
| 69 | PS_MIO32 | J16 | 70 | PS_MIO73 | G21 |
| 71 | GND | - | 72 | GND | - |
| 73 | PS_MIO46 | L20 | 74 | PS_MIO72 | G20 |
| 75 | PS_MIO50 | M19 | 76 | PS_MIO71 | B19 |
| 77 | GND | - | 78 | GND | - |
| 79 | PS_MIO49 | M18 | 80 | PS_MIO75 | A19 |
| 81 | PS_MIO34 | L17 | 82 | PS_MIO70 | C19 |
| 83 | GND | - | 84 | GND | - |
| 85 | PS_MIO26 | L15 | 86 | PS_MIO43 | K19 |
| 87 | PS_MIO24 | AB19 | 88 | PS_MIO51 | L21 |
| 89 | GND | - | 90 | GND | - |
| 91 | PS_MIO25 | AB21 | 92 | PS_MIO42 | L18 |
| 93 | - | - | 94 | PS_MIO33 | L16 |
| 95 | GND | - | 96 | GND | - |
| 97 | - | - | 98 | - | - |
| 99 | VCCO_65 | - | 100 | VCCO_66 | - |
| 101 | VCCO_65 | - | 102 | VCCO_66 | - |
| 103 | VCCO_65 | - | 104 | VCCO_66 | - |
| 105 | GND | - | 106 | GND | - |
| 107 | +12V | - | 108 | +12V | - |
| 109 | +12V | - | 110 | +12V | - |
| 111 | +12V | - | 112 | +12V | - |
| 113 | +12V | - | 114 | +12V | - |
| 115 | +12V | - | 116 | +12V | - |
| 117 | +12V | - | 118 | +12V | - |
| 119 | +12V | - | 120 | +12V | - |
Table 2.10.4 - J32 Connector Pin Assignment
Chapter 3 Carrier Board
3.1 Introduction
From the functional overview above, the functions of the carrier board can be seen as follows.
1 M.2 interface
1 DP output interface
4 USB3.0 interfaces
2 Gigabit Ethernet interfaces
2 USB UART interfaces
1 Micro SD card slot
1 MIPI camera interface
2 40-pin expansion ports
2 CAN communication interfaces
2 RS485 communication interfaces
JTAG debugging port
1 temperature sensor
1 EEPROM
1 RTC real-time clock
3 LEDs
3 push buttons
3.2 M.2 Interface
The AXU2CGB-I development board is equipped with one standard PCIe x1 M.2 interface for connecting an M.2 SSD, with a communication speed of up to 5Gbps. The M.2 interface uses an M-key slot and supports PCIe only, not SATA, so a PCIe SSD should be selected.
The PCIe signals are connected directly to the BANK505 PS MGT transceivers of the ZU2CG; one TX pair and one RX pair are connected to MGT LANE0 as differential signals. The PCIe clock is provided by the Si5332 chip at 100MHz. The M.2 circuit design is shown in Figure 3.2.1:
Figure 3.2.1 - M.2 Interface Design Diagram
The Zynq pin assignment of the M.2 interface is as follows:
| Signal Name | Pin Name | Pin Number | Remark |
| PCIe_TX_P | 505_TX0_P | E25 | PCIe data transmit positive |
| PCIe _TX_N | 505_TX0_N | E26 | PCIe data transmit negative |
| PCIe _RX_P | 505_RX0_P | F27 | PCIe data receive positive |
| PCIe _RX_N | 505_RX0_N | F28 | PCIe data receive negative |
| 505_PCIe_REFCLK_P | 505_CLK0_P | F23 | PCIe reference clock positive |
| 505_PCIe_REFCLK_N | 505_CLK0_N | F24 | PCIe reference clock negative |
| PCIe_RSTn_MIO37 | PS_MIO37_501 | J17 | PCIe reset signal |
Table 3.2.1 - M.2 Interface ZYNQ Pin Assignment
3.3 DP Display Interface
The AXU2CGB-I development board provides one standard Mini DisplayPort (mini DP) output interface for video image display. The interface supports the VESA DisplayPort V1.2a output standard and up to 4K@30Hz output, supports Y-only, YCbCr444, YCbCr422, YCbCr420 and RGB video formats, and supports 6, 8, 10 or 12 bits per color.
The DisplayPort data lanes are driven directly by the BANK505 PS MGT of the ZU2CG; the LANE2 and LANE3 TX signals of the MGT are connected to the DP connector as differential signals. The DisplayPort auxiliary channel is connected to the MIO pins of the PS. The DP output interface design is shown in Figure 3.3.1:
Figure 3.3.1 - DP Interface Design Diagram
The Zynq pin assignment of the DisplayPort interface is as follows:
| Signal Name | ZYNQ Pin Name | ZYNQ Pin Number | Remark |
| GT0_DP_TX_P | 505_TX3_P | B23 | DP data low-bit transmit positive |
| GT0_DP_TX_N | 505_TX3_N | B24 | DP data low-bit transmit negative |
| GT1_DP_TX_P | 505_TX2_P | C25 | DP data high-bit transmit positive |
| GT1_DP_TX_N | 505_TX2_N | C26 | DP data high-bit transmit negative |
| 505_CLK1_P | 505_CLK2_P | C21 | DP reference clock positive |
| 505_CLK1_N | 505_CLK2_N | C22 | DP reference clock negative |
| DP_AUX_OUT | PS_MIO27 | J15 | DP auxiliary data output |
| DP_AUX_IN | PS_MIO30 | F16 | DP auxiliary data input |
| DP_OE | PS_MIO29 | G16 | DP auxiliary data output enable |
| DP_HPD | PS_MIO28 | K15 | DP hot-plug detect |
Table 3.3.1 - DisplayPort Interface ZYNQ Pin Assignment
3.4 USB3.0 Interface
The AXU2CGB-I carrier board has four USB3.0 interfaces supporting HOST mode, with a data transfer speed of up to 5.0Gbps. USB3.0 is connected through the PS GTR transceiver (BANK505 LANE1) to the upstream port of the GL3523T HUB, which expands four USB3.0 interfaces; USB2.0 is connected to an external USB3320C chip through the ULPI interface, enabling high-speed USB3.0 and USB2.0 data communication.
The USB connectors are Type A receptacles, so that users can connect different USB slave peripherals at the same time (such as a USB mouse, keyboard or USB flash drive). The USB3.0 connection is shown in Figure 3.4.1:
Figure 3.4.1 - USB3.0 Interface Diagram
USB interface pin assignment:
| Signal Name | Pin Name | Pin Number | Remark |
| USB_SSTXP | 505_TX1_P | D23 | USB3.0 data transmit positive |
| USB_SSTXN | 505_TX1_N | D24 | USB3.0 data transmit negative |
| USB_SSRXP | 505_RX1_P | D27 | USB3.0 data receive positive |
| USB_SSRXN | 505_RX1_N | D28 | USB3.0 data receive negative |
| USB_DATA0 | PS_MIO56 | C16 | USB2.0 data bit0 |
| USB_DATA1 | PS_MIO57 | A16 | USB2.0 data bit1 |
| USB_DATA2 | PS_MIO54 | F17 | USB2.0 data bit2 |
| USB_DATA3 | PS_MIO59 | E17 | USB2.0 data bit3 |
| USB_DATA4 | PS_MIO60 | C17 | USB2.0 data bit4 |
| USB_DATA5 | PS_MIO61 | D17 | USB2.0 data bit5 |
| USB_DATA6 | PS_MIO62 | A17 | USB2.0 data bit6 |
| USB_DATA7 | PS_MIO63 | E18 | USB2.0 data bit7 |
| USB_STP | PS_MIO58 | F18 | USB2.0 stop signal |
| USB_DIR | PS_MIO53 | D16 | USB2.0 data direction signal |
| USB_CLK | PS_MIO52 | G18 | USB2.0 clock signal |
| USB_NXT | PS_MIO55 | B16 | USB2.0 next data signal |
| USB_RESET_N | PS_MIO31 | H16 | USB2.0 reset signal |
Table 3.4.1 - USB Interface Pin Assignment
3.5 Gigabit Ethernet Interface
The AXU2CGB-I carrier board has two Gigabit Ethernet interfaces, one connected to the PS side and the other to the PL side. The Ethernet chips are industrial-grade Ethernet PHY chips from JLSemi (JL2121-N040I), providing network communication for users. The PS-side Ethernet PHY is connected to the MIO pins of BANK502 on the PS side of the Zynq, and the PL-side Ethernet PHY is connected to the IO of BANK66. The JL2121 supports 10/100/1000 Mbps network transmission rates and communicates with the MAC layer of the MPSoC system through the RGMII interface. The JL2121 supports MDI/MDX auto-detection, auto-negotiation of all speeds and master/slave auto-detection, and supports the MDIO bus for PHY register management.
On power-up the JL2121 detects the level of certain IO pins to determine its operating mode. Table 3.5.1 describes the default settings of the PHY chip after power-up.
| Configuration Pin | Description | Configuration Value |
| RXD3_ADR0 RXC_ADR1 RXCTL_ADR2 | PHY address in MDIO/MDC mode | PHY address is 001 |
| RXD1_TXDLY | TX clock 2ns delay | Delay |
| RXD0_RXDLY | RX clock 2ns delay | Delay |
Table 3.5.1 - Default Configuration Values of the PHY Chip
When the network is connected at Gigabit Ethernet, data is transferred between the MPSoC and the PHY chip JL2121 over the RGMII bus with a 125MHz transfer clock, and data is sampled on both the rising and falling edges of the clock.
When the network is connected at 100Mbps Ethernet, data is transferred between the MPSoC and the PHY chip JL2121 over the RGMII bus with a 25MHz transfer clock, and data is sampled on both the rising and falling edges of the clock. Figure 3.5.1 shows the connection between the MPSoC and the Ethernet PHY chip:
Figure 3.5.1 - ZYNQ to GPHY Connection Diagram
The Gigabit Ethernet pin assignment is as follows:
| Signal Name | Pin Name | Pin Number | Remark |
| PHY1_TXCK | PS_MIO64 | E19 | Ethernet 1 RGMII transmit clock |
| PHY1_TXD0 | PS_MIO65 | A18 | Ethernet 1 transmit data bit0 |
| PHY1_TXD1 | PS_MIO66 | G19 | Ethernet 1 transmit data bit1 |
| PHY1_TXD2 | PS_MIO67 | B18 | Ethernet 1 transmit data bit2 |
| PHY1_TXD3 | PS_MIO68 | C18 | Ethernet 1 transmit data bit3 |
| PHY1_TXCTL | PS_MIO69 | D19 | Ethernet 1 transmit enable |
| PHY1_RXCK | PS_MIO70 | C19 | Ethernet 1 RGMII receive clock |
| PHY1_RXD0 | PS_MIO71 | B19 | Ethernet 1 receive data bit0 |
| PHY1_RXD1 | PS_MIO72 | G20 | Ethernet 1 receive data bit1 |
| PHY1_RXD2 | PS_MIO73 | G21 | Ethernet 1 receive data bit2 |
| PHY1_RXD3 | PS_MIO74 | D20 | Ethernet 1 receive data bit3 |
| PHY1_RXCTL | PS_MIO75 | A19 | Ethernet 1 receive data valid |
| PHY1_MDC | PS_MIO76 | B20 | Ethernet 1 MDIO management clock |
| PHY1_MDIO | PS_MIO77 | F20 | Ethernet 1 MDIO management data |
| PHY2_TXCK | B66_L21_P | A7 | Ethernet 2 RGMII transmit clock |
| PHY2_TXD0 | B66_L18_P | E9 | Ethernet 2 transmit data bit0 |
| PHY2_TXD1 | B66_L18_N | D9 | Ethernet 2 transmit data bit1 |
| PHY2_TXD2 | B66_L23_P | A9 | Ethernet 2 transmit data bit2 |
| PHY2_TXD3 | B66_L23_N | A8 | Ethernet 2 transmit data bit3 |
| PHY2_TXCTL | B66_L24_N | B9 | Ethernet 2 transmit enable |
| PHY2_RXCK | B66_L14_P | E5 | Ethernet 2 RGMII receive clock |
| PHY2_RXD0 | B66_L19_N | A5 | Ethernet 2 receive data bit0 |
| PHY2_RXD1 | B66_L19_P | B5 | Ethernet 2 receive data bit1 |
| PHY2_RXD2 | B66_L17_P | F8 | Ethernet 2 receive data bit2 |
| PHY2_RXD3 | B66_L24_P | C9 | Ethernet 2 receive data bit3 |
| PHY2_RXCTL | B66_L22_N | B8 | Ethernet 2 receive data valid |
| PHY2_MDC | B66_L21_N | A6 | Ethernet 2 MDIO management clock |
| PHY2_MDIO | B66_L22_P | C8 | Ethernet 2 MDIO management data |
| PHY2_RESET | B66_L14_N | D5 | Ethernet 2 reset signal |
Table 3.5.2 - Gigabit Ethernet Pin Assignment
3.6 USB UART Interface
The AXU2CGB-I carrier board is equipped with two USB UART interfaces, one connected to the PS side and one to the PL side. The converter chips are Silicon Labs CP2102GM USB-UART chips and the USB connectors are MINI USB connectors, so a USB cable can connect the board to the USB port of a PC for serial data communication. The USB UART circuit is shown below.
Figure 3.6.1 - USB UART Interface Diagram
The Zynq pin assignment of the USB UART interfaces is as follows:
| Signal Name | Pin Name | Pin Number | Remark |
| PS_UART0_TX | PS_MIO43 | K19 | PS UART data output |
| PS_UART0_RX | PS_MIO42 | L18 | PS UART data input |
| PL_UART_TX | B43_L3_P | AH12 | PL UART data output |
| PL_UART_RX | B43_L3_N | AH11 | PL UART data input |
Table 3.6.1 - ZYNQ Pin Assignment of the USB UART Interface
3.7 Micro SD Card Slot
The AXU2CGB-I carrier board includes one Micro SD card slot that gives users access to Micro SD card storage, used for storing the BOOT program of the ZU2CG, the Linux kernel, the file system and other user data files.
The SDIO signals are connected to the IO signals of PS BANK501 of the ZU2CG. Because the VCCIO of BANK501 is set to 1.8V while the data level of the Micro SD card is 3.3V, a TXS02612 level shifter is used for the connection. The schematic between the ZU2CG PS and the Micro SD card connector is shown in Figure 3.7.1.
Figure 3.7.1 - SD Card Connection Diagram
The pin assignment of the Micro SD card slot is shown in the table below:
| Signal Name | Pin Name | Pin Number | Remark |
| SD_CLK | PS_MIO51 | l21 | SD clock signal |
| SD_CMD | PS_MIO50 | M19 | SD command signal |
| SD_D0 | PS_MIO46 | L20 | SD data Data0 |
| SD_D1 | PS_MIO47 | H21 | SD data Data1 |
| SD_D2 | PS_MIO48 | J21 | SD data Data2 |
| SD_D3 | PS_MIO49 | M18 | SD data Data3 |
| SD_CD | PS_MIO45 | K20 | SD card detect signal |
Table 3.7.1 - Micro SD Card Slot Pin Assignment
3.8 40-Pin Expansion Port
The AXU2CGB-I carrier board reserves two 40-pin expansion ports J15 and J16 with a standard 2.54mm pitch, used to connect various ALINX modules or user-designed external circuits. Each expansion port carries 40 signals, including one 5V power supply, two 3.3V power supplies, three grounds and 34 IO pins. The IO pins of the expansion ports are connected to the IO of BANK43, 44, 45 and 46 of the Zynq chip, with a 3.3V level standard. The Zynq pin assignment of expansion port J16 is as follows:
| J16 Pin | Signal Name | Pin Number | J16 Pin | Signal Name | Pin Number |
| 1 | GND | - | 2 | +5V | - |
| 3 | B45_L9_N | B10 | 4 | B45_L9_P | C11 |
| 5 | B45_L5_N | F10 | 6 | B45_L5_P | G11 |
| 7 | B45_L12_N | C12 | 8 | B45_L12_P | D12 |
| 9 | B45_L11_N | A11 | 10 | B45_L11_P | A12 |
| 11 | B45_L6_N | F11 | 12 | B45_L6_P | F12 |
| 13 | B46_L6_N | E13 | 14 | B46_L6_P | E14 |
| 15 | B46_L3_N | A13 | 16 | B46_L3_P | B13 |
| 17 | B46_L2_N | A14 | 18 | B46_L2_P | B14 |
| 19 | B46_L4_N | C13 | 20 | B46_L4_P | C14 |
| 21 | B46_L12_N | L13 | 22 | B46_L12_P | L14 |
| 23 | B45_L4_N | H12 | 24 | B45_L4_P | J12 |
| 25 | B46_L11_N | J14 | 26 | B46_L11_P | K14 |
| 27 | B46_L10_N | H13 | 28 | B46_L10_P | H14 |
| 29 | B46_L7_N | F13 | 30 | B46_L7_P | G13 |
| 31 | B46_L9_N | G14 | 32 | B46_L9_P | G15 |
| 33 | B46_L5_N | D14 | 34 | B46_L5_P | D15 |
| 35 | B46_L1_N | A15 | 36 | B46_L1_P | B15 |
| 37 | GND | - | 38 | GND | - |
| 39 | +3.3V | - | 40 | +3.3V | - |
Table 3.8.1 - ZYNQ Pin Assignment of Expansion Port J16
The Zynq pin assignment of expansion port J15 is as follows:
| J15 Pin | Signal Name | Pin Number | J15 Pin | Signal Name | Pin Number |
| 1 | GND | - | 2 | +5V | - |
| 3 | B43_L2_N | AG11 | 4 | B43_L2_P | AF11 |
| 5 | B44_L8_N | AB14 | 6 | B44_L8_P | AB15 |
| 7 | B44_L9_N | W13 | 8 | B44_L9_P | W14 |
| 9 | B44_L11_N | W11 | 10 | B44_L11_P | W12 |
| 11 | B43_L10_N | Y10 | 12 | B43_L10_P | W10 |
| 13 | B43_L12_N | AB9 | 14 | B43_L12_P | AB10 |
| 15 | B44_L3_N | AH13 | 16 | B44_L3_P | AG13 |
| 17 | B44_L12_N | AA12 | 18 | B44_L12_P | Y12 |
| 19 | B44_L1_N | AE14 | 20 | B44_L1_P | AE15 |
| 21 | B44_L5_N | AD14 | 22 | B44_L5_P | AD15 |
| 23 | B44_L6_N | AC13 | 24 | B44_L6_P | AC14 |
| 25 | B44_L10_N | Y13 | 26 | B44_L10_P | Y14 |
| 27 | B44_L2_N | AH14 | 28 | B44_L2_P | AG14 |
| 29 | B43_L8_N | AC11 | 30 | B43_L8_P | AB11 |
| 31 | B43_L7_N | AD10 | 32 | B43_L7_P | AD11 |
| 33 | B43_L6_N | AD12 | 34 | B43_L6_P | AC12 |
| 35 | B44_L7_N | AB13 | 36 | B44_L7_P | AA13 |
| 37 | GND | - | 38 | GND | - |
| 39 | +3.3V | - | 40 | +3.3V | - |
Table 3.8.2 - ZYNQ Pin Assignment of Expansion Port J15
3.9 CAN Communication Interface
The AXU2CGB-I carrier board has two CAN communication interfaces connected to the MIO pins of BANK501 on the PS side. The CAN transceivers are TI SN65HVD232, providing CAN communication for users. Figure 3.9.1 shows the connection of the PS-side CAN transceivers.
Figure 3.9.1 - Connection Diagram of the PS-Side CAN Transceivers
The CAN communication pin assignment is as follows:
| Signal Name | Pin Name | Pin Number | Remark |
| PS_CAN1_TX | PS_MIO32 | J16 | CAN1 transmit |
| PS_CAN1_RX | PS_MIO33 | L16 | CAN1 receive |
| PS_CAN2_TX | PS_MIO39 | H19 | CAN2 transmit |
| PS_CAN2_RX | PS_MIO38 | H18 | CAN2 receive |
Table 3.9.1 - CAN Communication Pin Assignment
3.10 RS485 Communication Interface
The AXU2CGB-I carrier board has two RS485 communication interfaces connected to the IO of BANK43 to BANK45 on the PL side. The RS485 transceivers are MAXIM MAX3485, providing RS485 communication for users. Figure 3.10.1 shows the connection of the PL-side RS485 transceivers.
Figure 3.10.1 - Connection Diagram of the PL-Side RS485 Communication
The RS485 communication pin assignment is as follows:
| Signal Name | Pin Name | Pin Number | Remark |
| PL_485_TXD1 | B43_L1_N | AH10 | RS485 channel 1 transmit |
| PL_485_RXD1 | B44_L4_P | AE13 | RS485 channel 1 receive |
| PL_485_DE1 | B45_L10_P | B11 | RS485 channel 1 transmit enable |
| PL_485_TXD2 | B43_L1_P | AG10 | RS485 channel 2 transmit |
| PL_485_RXD2 | B44_L4_N | AF13 | RS485 channel 2 receive |
| PL_485_DE2 | B45_L10_N | A10 | RS485 channel 2 transmit enable |
Table 3.10.1 - RS485 Communication Pin Assignment
3.11 MIPI Interface
The carrier board has one MIPI camera interface, to which a MIPI OV5640 camera module (AN5641) can be connected. The MIPI interface uses a 15-pin FPC connector and carries two data lanes plus one clock pair, connected to the differential IO pins of BANK65 with a 1.2V level standard; the other control signals are connected to the IO of BANK43 with a 3.3V level standard.
Figure 3.11.1 - MIPI Interface Design Schematic
The MIPI interface pin assignment is shown in the table below:
| Signal Name | ZYNQ Pin Name | ZYNQ Pin Number | Remark |
| MIPI_CLK_P | B65_L1_P | W8 | MIPI input clock positive |
| MIPI_CLK_N | B65_L1_N | Y8 | MIPI input clock negative |
| MIPI_LAN0_P | B65_L2_P | U9 | MIPI input data LANE0 positive |
| MIPI_LAN0_N | B65_L2_N | V9 | MIPI input data LANE0 negative |
| MIPI_LAN1_P | B65_L3_P | U8 | MIPI input data LANE1 positive |
| MIPI_LAN1_N | B65_L3_N | V8 | MIPI input data LANE1 negative |
| CAM_GPIO | B43_L4_P | AE10 | Camera GPIO control |
| CAM_CLK | B43_L4_N | AF10 | Camera clock input |
| CAM_SCL | B43_L11_P | Y9 | Camera I2C clock |
| CAM_SDA | B43_L11_N | AA8 | Camera I2C data |
Table 3.11.1 - MIPI Interface Pin Assignment
3.12 JTAG Debugging Port
A JTAG interface is reserved on the AXU2CGB-I carrier board for downloading Zynq UltraScale+ programs or programming the configuration into FLASH. To prevent damage to the Zynq UltraScale+ caused by hot plugging, protection diodes have been added on the JTAG signals to keep the signal voltage within the range accepted by the FPGA, thus avoiding damage to the Zynq UltraScale+.
3.13 RTC Real-Time Clock
The ZU2CG has a built-in RTC real-time clock function with year, month, day, hour, minute and second, as well as day-of-week counting. An external 32.768kHz passive clock is required to provide an accurate clock source for the internal clock circuit, so that the RTC can keep accurate time. In addition, so that the real-time clock keeps running after the product is powered down, a battery is normally used to supply the clock chip. BT1 on the development board is a 1.5V coin-cell battery (model LR1130); when the system power is removed, the coin-cell battery continues to supply the RTC system and provides continuous time information. Figure 3.13.1 is the RTC schematic.
Figure 3.13.1 - RTC Real-Time Clock Schematic
3.14 EEPROM and Temperature Sensor
The AXU2CGB-I development board carries one EEPROM, model 24LC04, with a capacity of 4Kbit (22568 bits), connected to the PS side through the I2C bus. The board also carries a high-precision, low-power digital temperature sensor, the ON Semiconductor LM75, with a temperature accuracy of 0.5 degree. The EEPROM and the temperature sensor are attached to the BANK500 MIO of the Zynq UltraScale+ through the I2C bus. Figure 3.14.1 is the schematic of the EEPROM and the temperature sensor.
Figure 3.14.1 - Schematic of the EEPROM and the Sensor
The EEPROM communication pin assignment is as follows:
| Signal Name | Pin Name | Pin Number | Remark |
| PS_IIC1_SCL | PS_MIO24 | AB19 | I2C clock signal |
| PS_IIC1_SDA | PS_MIO25 | AB21 | I2C data signal |
Table 3.14.1 - EEPROM Communication Pin Assignment
3.15 LEDs
The AXU2CGB-I carrier board has three light-emitting diodes, one power indicator, one PS control indicator and one PL control indicator (hereinafter referred to as user LEDs), whose on/off state can be controlled by the program. When the voltage of the control IO is low, the user LED is off; when the voltage of the control IO is high, the user LED is on. The hardware connection of the user LEDs is shown in Figure 3.15.1:
Figure 3.15.1 - Hardware Connection of the User LEDs
The pin assignment of the user LEDs is as follows:
| Signal Name | Pin Name | Pin Number | Remark |
| PS_LED1 | PS_MIO40 | K18 | User PS LED |
| PL_LED1 | B43_L5_P | AE12 | User PL LED |
Table 3.15.1 - Pin Assignment of the User LEDs
3.16 Push Buttons
The AXU2CGB-I carrier board has one reset button RESET and two user buttons. The reset signal is connected to the input of the reset chip on the SoM, so users can use this reset button to reset the Zynq system. One user button is connected to the MIO of the PS and the other to the IO of the PL. Both the reset button and the user buttons are active low. The connection of the push buttons is shown in Figure 3.16.1:
Figure 3.16.1 - Reset Button Connection Diagram
The Zynq pin assignment of the push buttons is shown in the table below:
| Signal Name | Pin Name | Pin Number | Remark |
| PS_KEY1 | PS_MIO26 | L15 | PS button 1 input |
| PL_KEY1 | B43_L5_N | AF12 | PL button 1 input |
Table 3.16.1 - ZYNQ Pin Assignment of the Push Buttons
3.17 DIP Switch Configuration
The development board has a 4-position DIP switch SW1 that configures the boot mode of the Zynq system. The AXU2CGB-I development platform supports four boot modes: JTAG debugging mode, QSPI FLASH, eMMC and SD2.0 card boot. After power-up the ZU2CG detects the level of PS_MODE0 to PS_MODE3 to decide which boot mode to use. Users can select a boot mode with the DIP switch SW1 on the carrier board. The SW1 boot mode configuration is shown in Table 3.17.1.
| SW1 | Switch position (1, 2, 3, 4) | MODE[3:0] | Boot Mode |
| ON, ON, ON, ON | 0000 | PS JTAG |
| ON, ON, OFF ,ON | 0010 | QSPI FLASH | |
| ON, OFF, ON, OFF | 0101 | SD Card | |
| ON, OFF, OFF, ON | 0110 | EMMC |
Table 3.17.1 - SW1 Boot Mode Configuration
3.18 Power Supply
The supply input voltage of the AXU2CGB-I development board is DC12V. On the carrier board, one DC/DC regulator TPS54620 and two DC/DC regulators MP1482 convert the input into +5V, +3.3V and +1.8V. In addition, an LDO on the carrier board generates +1.2V to supply BANK65 of the SoM, while BANK66 is supplied with +1.8V. The power design on the board is shown in Figure 3.18.1:
Figure 3.18.1 - Power Interface Section of the Schematic
The functions of the individual supplies are listed in the table below:
| Power Supply | Function |
| +5.0V | USB power supply |
| +1.8V | Ethernet, USB2.0, BANK66 of the SoM |
| +3.3V | Ethernet, USB2.0, SD, DP, CAN, RS485 |
| +1.2V | BANK65 of the SoM |
Table 3.18.1 - Power Supply Function Assignment
3.19 Fan
Because the ZU2CG generates a large amount of heat during normal operation, a heatsink and a fan have been added on the board to prevent the chip from overheating. The fan is controlled by the Zynq chip, with the control pin connected to the IO of BANK43 (AA11). When the IO output is high, the MOSFET conducts and the fan runs; when the IO output is low, the fan stops. The fan is fixed to the development board with screws before delivery, and its power is connected to the J42 socket, with the red wire as positive and the black wire as negative.
3.20 Mechanical Dimensions
Figure 3.20.1 - Mechanical Dimensions
Appendix: List of Abbreviations
| Abbreviation | Full English Name | Description |
| PS | Processor System | The processing subsystem in an SoC, typically including CPU cores, memory controllers, and peripheral interfaces. |
| PL | Programmable Logic | User-configurable FPGA logic resources for implementing custom digital circuits and hardware acceleration. |
| SoC | System on Chip | An integrated circuit combining processors, memory controllers, and peripheral interfaces on a single chip. |
| DDR4 | Double Data Rate 4 SDRAM | Fourth-generation synchronous dynamic memory technology transferring data on both clock edges. |
| eMMC | Embedded Multi Media Card | An embedded non-volatile storage device integrating NAND Flash and a controller in one package. |
| QSPI | Quad Serial Peripheral Interface | A high-speed serial interface using four data lines, commonly used for NOR Flash boot devices. |
| GTH | Gigabit Transceiver | High-speed serial transceivers in Xilinx FPGAs supporting multi-gigabit data rates. |
| UART | Universal Asynchronous Receiver/Transmitter | An asynchronous serial communication interface using TX and RX lines. |
| DP | DisplayPort | A digital display interface standard for video and audio transmission. |
| PCIe | Peripheral Component Interconnect Express | A high-speed serial expansion bus standard. |
| USB | Universal Serial Bus | A standard serial interface for data communication and power delivery. |
| JTAG | Joint Test Action Group | A standardized interface for device testing, boundary scan, and FPGA programming. |
| QSFP+ | Quad Small Form-factor Pluggable Plus | A high-density hot-pluggable optical transceiver supporting up to 40Gbps. |
| MIO | Multiplexed I/O | Multiplexed processor I/O pins configurable as UART, I2C, SPI, or GPIO. |
| PHY | Physical Layer Transceiver | An analog front-end device that converts digital data to/from physical network signals. |
| I2C | Inter-Integrated Circuit | A two-wire serial bus using SDA and SCL for connecting peripherals. |
| RGMII | Reduced Gigabit Media Independent Interface | A reduced-pin-count Ethernet MAC-to-PHY interface supporting up to 1000Mbps. |
| FMC | FPGA Mezzanine Card | A standard mezzanine connector for FPGA I/O expansion. |
| LED | Light Emitting Diode | A semiconductor device that emits light, used for status indication. |
| CANFD | Controller Area Network Flexible Data Rate | An upgraded CAN bus standard supporting flexible data rates up to 5Mbps. |
| GPS | Global Positioning System | A satellite-based navigation system providing location and time synchronization. |
| EEPROM | Electrically Erasable Programmable Read-Only Memory | A non-volatile memory that can be erased and rewritten electrically. |
| DDR | Double Data Rate | Memory technology transferring data on both rising and falling clock edges. |
| PMIC | Power Management IC | A chip that integrates multiple power conversion and management functions. |
Contact information
Alinx Electronic Limited
Company Website: www.en.alinx.com
Service Hotline: +86 21 67676997
Technical Support:technical@alinx.com