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DZ7 User Manual
Alinx Electronic Limited
Company Website: www.en.alinx.com
Service Hotline: +86 21 67676997
Technical Support : technical@alinx.com
Document Information
| Item | Content |
| Document Name | User Manual |
| Product Model | DZ7 |
| Document Version | V1.0 |
| Prepared by | Alinx Electronic Limited |
| Release Date | 2026.11.2 |
Document Revision History
| Version | Date | Section | Revision Summary |
| V1.0 | 2026.11.2 | All | Initial release |
Introduction
Alinx Electronic Limited officially releases the DZ7 development platform based on the Xilinx Zynq UltraScale+ MPSoCs. This user manual is designed to help you quickly understand the development platform. The DZ7 MPSoC development platform uses the Xilinx Zynq UltraScale+ EV family chip ZU7EV, which integrates a quad-core ARM Cortex-A53 processor and FPGA programmable logic on a single chip using Processing System (PS) + Programmable Logic (PL) technology.
The DZ7 features four 1GB high-speed DDR4 SDRAM chips (4GB total) on the PS side, one 8GB eMMC flash memory chip, and two 256Mbit QSPI flash chips. The carrier board expands a rich set of peripheral interfaces, including 2x FMC HPC, 1x M.2 SSD interface, 1x Mini DP interface, 1x USB3.0 Type-C interface, 2x Gigabit Ethernet interfaces, 1x CANFD and GPS interface, 1x QSFP+ optical fiber interface, and 1x Micro SD card slot.
The DZ7 platform supports high-speed data exchange, data storage, video transmission and processing, and serves as a modular product carrier for vertical industries such as automotive applications. Based on the AMD MPSoC ZU7EV with 2x FMC interfaces, it can be used to build automotive ECU aging testing and similar products. It is a professional-grade Zynq development platform that enables early verification and later application of high-speed data transmission, data exchange, and data processing.
Figure 1.1 DZ7 Development Board Photo
Figure 1.2 DZ7 System Block Diagram
The DZ7 platform features the following interfaces and functions:
Xilinx ARM+FPGA chip XCZU7EV-2FFVC1156I.
DDR4: Four 1GB (4GB total) high-speed DDR4 SDRAM chips on the PS side.
eMMC: One 8GB eMMC flash memory chip on the PS side for storing operating system files and user data.
QSPI Flash: Two 256Mbit QSPI flash chips for storing U-Boot, system files, and user data.
M.2 interface: 1x PCIe x1 M.2 interface for connecting M.2 SSDs, with up to 5Gbps per lane.
DP output: 1x standard DisplayPort output for video display, supporting up to 4K@30Hz or 1080P@60Hz.
USB3.0: 1x USB3.0 Type-C interface, supporting HOST, SLAVE, and OTG modes.
Gigabit Ethernet: 2x PS-side 10/100/1000 Mbps RJ45 Ethernet interfaces for data exchange.
QSFP+: 4x high-speed GTH transceivers connected to one QSFP+ optical module interface, supporting up to 40Gbps fiber communication.
Micro SD card slot: 1x Micro SD card slot for storing operating system images and file systems.
CANFD and GPS: 2x CAN bus interfaces using NXP TJA1051T/3 transceivers; GPS signals connected to FPGA through level shifters; CANFD and GPS share a 10-pin external connector.
FMC expansion: 2x standard FMC HPC connectors supporting various Alinx or Xilinx FMC modules (HDMI in/out, GMSL video capture, GMSL video injection, etc.).
JTAG: 1x 14-pin 2.54mm standard JTAG port for FPGA programming and debugging using Xilinx download cables.
EEPROM: 1x I2C EEPROM (24LC04).
LEDs: 4x user LEDs and 1x dual-color LED. The board has 1x power indicator, 1x DONE configuration indicator, 2x user LEDs, and the dual-color LED is connected to the PS side.
Buttons: 1x side reset button and 1x side power button.
Zynq Chip
The DZ7 development board uses the Xilinx Zynq UltraScale+ MPSoCs EV series chip, model XCZU7EV-2FFVC1156I. The ZU7EV PS system integrates 4x ARM Cortex-A53 processors up to 1.3GHz with 2-level cache, and also includes 2x Cortex-R5 processors up to 533MHz.
The ZU7EV chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L, and LPDDR3 memory. The PS side provides rich high-speed interfaces such as PCIe Gen2, USB3.0, SATA 3.1, and DisplayPort, as well as USB2.0, Gigabit Ethernet, SD/SDIO, I2C, CAN, UART, and GPIO. The PL side contains abundant programmable logic cells, DSP slices, and internal RAM. The ZU7EV block diagram is shown in Figure 2.1.
Figure 2.1 ZU7EV Block Diagram
The main PS system specifications are as follows: Quad-core ARM Cortex-A53 processor, up to 1.3GHz, with 32KB Level-1 instruction and data cache per CPU and a 1MB Level-2 cache shared by two CPUs. Dual-core ARM Cortex-R5 processor, up to 533MHz, with 32KB Level-1 instruction and data cache per CPU and 128KB tightly-coupled memory. Mali-400 MP2 graphics processor, up to 677MHz, with 64KB Level-2 cache. External memory interface supporting 32/64-bit DDR4/DDR3/DDR3L and LPDDR4/LPDDR3. Static memory interface supporting NAND and 2x Quad-SPI Flash. High-speed connectivity supporting PCIe Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, and 4x Tri-mode Gigabit Ethernet. General connectivity: 2x USB2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, and 4x 32-bit GPIO. Power management: supports power partitioning across Full/Low/PL/Battery domains. Cryptography: supports RSA, AES, and SHA. System monitor: a 10-bit 1MHz ADC for temperature and voltage monitoring.
Quad-core ARM Cortex-A53 processor up to 1.3GHz, 32KB L1 instruction and data cache per CPU, 1MB L2 cache shared by 2 CPUs.
Dual-core ARM Cortex-R5 processor up to 533MHz, 32KB L1 cache per CPU, and 128KB tightly coupled memory.
Mali-400 MP2 graphics processor up to 677MHz with 64KB L2 cache.
External memory interface: 32/64-bit DDR4/3/3L, LPDDR4/3.
Static memory interface: NAND, 2x Quad-SPI Flash.
High-speed connectivity: PCIe Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet.
General connectivity: 2x USB2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32-bit GPIO.
Power management: Full/Low/PL/Battery four-domain power architecture.
Security: RSA, AES, and SHA encryption.
System monitoring: 10-bit 1MSPS ADC for temperature and voltage sensing.
The main PL logic specifications are as follows: System Logic Cells: 504K; CLB flip-flops: 460.8K; CLB LUTs: 230.4K; Block RAM: 11Mbit; Clock Management Tiles (CMTs): 8; DSP Slices: 1728; GTH 16.3Gbps transceivers: 20.
System Logic Cells: 504K
CLB Flip-Flops: 460.8K
CLB LUTs: 230.4K
Block RAM: 11Mbit
Clock Management Tiles (CMTs): 8
DSP Slices: 1728
GTH 16.3Gbps transceivers: 20
The XCZU7EV-2FFVC1156I chip has a speed grade of -2, industrial temperature range, and FFVC1156 package.
DDR4 DRAM
The DZ7 is equipped with four 1GB Micron DDR4 chips, model MT40A512M16LY-062E. All four chips are mounted on the PS side, forming a 64-bit data bus with 4GB total capacity. The PS-side DDR4 SDRAM runs up to 1200MHz (2400Mbps data rate) and connects directly to the PS BANK504 memory interface. The configuration is shown in Table 3.1.
| Location | Reference Designator | Chip Model | Capacity | Manufacturer |
| PS | U4, U5, U6, U7 | MT40A512M16LY-062E | 512M x 16bit | Micron |
Table 3.1 DDR4 SDRAM Configuration
DDR4 hardware design requires careful signal integrity considerations. We have fully accounted for matching/termination resistors, trace impedance control, and length matching in the circuit and PCB design to ensure stable high-speed DDR4 operation.
The PS-side DDR4 SDRAM hardware connection is shown in Figure 3.1:
Figure 3.1 PS-side DDR4 DRAM Schematic
PS-side DDR4 SDRAM pin assignment:
| Signal Name | Pin Name | Pin Number |
| PS_DDR4_DQS0_N | PS_DDR_DQS_N0_504 | AN27 |
| PS_DDR4_DQS0_P | PS_DDR_DQS_P0_504 | AN26 |
| PS_DDR4_DQS1_N | PS_DDR_DQS_N1_504 | AP30 |
| PS_DDR4_DQS1_P | PS_DDR_DQS_P1_504 | AN29 |
| PS_DDR4_DQS2_N | PS_DDR_DQS_N2_504 | AJ26 |
| PS_DDR4_DQS2_P | PS_DDR_DQS_P2_504 | AH26 |
| PS_DDR4_DQS3_N | PS_DDR_DQS_N3_504 | AK29 |
| PS_DDR4_DQS3_P | PS_DDR_DQS_P3_504 | AK28 |
| PS_DDR4_DQS4_N | PS_DDR_DQS_N4_504 | AD31 |
| PS_DDR4_DQS4_P | PS_DDR_DQS_P4_504 | AD30 |
| PS_DDR4_DQS5_N | PS_DDR_DQS_N5_504 | Y28 |
| PS_DDR4_DQS5_P | PS_DDR_DQS_P5_504 | Y27 |
| PS_DDR4_DQS6_N | PS_DDR_DQS_N6_504 | AB34 |
| PS_DDR4_DQS6_P | PS_DDR_DQS_P6_504 | AB33 |
| PS_DDR4_DQS7_N | PS_DDR_DQS_N7_504 | W32 |
| PS_DDR4_DQS7_P | PS_DDR_DQS_P7_504 | W31 |
| PS_DDR4_DQ0 | PS_DDR_DQ0_504 | AP27 |
| PS_DDR4_DQ1 | PS_DDR_DQ1_504 | AP25 |
| PS_DDR4_DQ2 | PS_DDR_DQ2_504 | AP26 |
| PS_DDR4_DQ3 | PS_DDR_DQ3_504 | AM26 |
| PS_DDR4_DQ4 | PS_DDR_DQ4_504 | AP24 |
| PS_DDR4_DQ5 | PS_DDR_DQ5_504 | AL25 |
| PS_DDR4_DQ6 | PS_DDR_DQ6_504 | AM25 |
| PS_DDR4_DQ7 | PS_DDR_DQ7_504 | AM24 |
| PS_DDR4_DQ8 | PS_DDR_DQ8_504 | AM28 |
| PS_DDR4_DQ9 | PS_DDR_DQ9_504 | AN28 |
| PS_DDR4_DQ10 | PS_DDR_DQ10_504 | AP29 |
| PS_DDR4_DQ11 | PS_DDR_DQ11_504 | AP28 |
| PS_DDR4_DQ12 | PS_DDR_DQ12_504 | AM31 |
| PS_DDR4_DQ13 | PS_DDR_DQ13_504 | AP31 |
| PS_DDR4_DQ14 | PS_DDR_DQ14_504 | AN31 |
| PS_DDR4_DQ15 | PS_DDR_DQ15_504 | AM30 |
| PS_DDR4_DQ16 | PS_DDR_DQ16_504 | AF25 |
| PS_DDR4_DQ17 | PS_DDR_DQ17_504 | AG25 |
| PS_DDR4_DQ18 | PS_DDR_DQ18_504 | AG26 |
| PS_DDR4_DQ19 | PS_DDR_DQ19_504 | AJ25 |
| PS_DDR4_DQ20 | PS_DDR_DQ20_504 | AG24 |
| PS_DDR4_DQ21 | PS_DDR_DQ21_504 | AK25 |
| PS_DDR4_DQ22 | PS_DDR_DQ22_504 | AJ24 |
| PS_DDR4_DQ23 | PS_DDR_DQ23_504 | AK24 |
| PS_DDR4_DQ24 | PS_DDR_DQ24_504 | AH28 |
| PS_DDR4_DQ25 | PS_DDR_DQ25_504 | AH27 |
| PS_DDR4_DQ26 | PS_DDR_DQ26_504 | AJ27 |
| PS_DDR4_DQ27 | PS_DDR_DQ27_504 | AK27 |
| PS_DDR4_DQ28 | PS_DDR_DQ28_504 | AL26 |
| PS_DDR4_DQ29 | PS_DDR_DQ29_504 | AL27 |
| PS_DDR4_DQ30 | PS_DDR_DQ30_504 | AH29 |
| PS_DDR4_DQ31 | PS_DDR_DQ31_504 | AL28 |
| PS_DDR4_DQ32 | PS_DDR_DQ32_504 | AB29 |
| PS_DDR4_DQ33 | PS_DDR_DQ33_504 | AB30 |
| PS_DDR4_DQ34 | PS_DDR_DQ34_504 | AC29 |
| PS_DDR4_DQ35 | PS_DDR_DQ35_504 | AD32 |
| PS_DDR4_DQ36 | PS_DDR_DQ36_504 | AC31 |
| PS_DDR4_DQ37 | PS_DDR_DQ37_504 | AE30 |
| PS_DDR4_DQ38 | PS_DDR_DQ38_504 | AC28 |
| PS_DDR4_DQ39 | PS_DDR_DQ39_504 | AE29 |
| PS_DDR4_DQ40 | PS_DDR_DQ40_504 | AC27 |
| PS_DDR4_DQ41 | PS_DDR_DQ41_504 | AA27 |
| PS_DDR4_DQ42 | PS_DDR_DQ42_504 | AA28 |
| PS_DDR4_DQ43 | PS_DDR_DQ43_504 | AB28 |
| PS_DDR4_DQ44 | PS_DDR_DQ44_504 | W27 |
| PS_DDR4_DQ45 | PS_DDR_DQ45_504 | W29 |
| PS_DDR4_DQ46 | PS_DDR_DQ46_504 | W28 |
| PS_DDR4_DQ47 | PS_DDR_DQ47_504 | V27 |
| PS_DDR4_DQ48 | PS_DDR_DQ48_504 | AA32 |
| PS_DDR4_DQ49 | PS_DDR_DQ49_504 | AA33 |
| PS_DDR4_DQ50 | PS_DDR_DQ50_504 | AA34 |
| PS_DDR4_DQ51 | PS_DDR_DQ51_504 | AE34 |
| PS_DDR4_DQ52 | PS_DDR_DQ52_504 | AD34 |
| PS_DDR4_DQ53 | PS_DDR_DQ53_504 | AB31 |
| PS_DDR4_DQ54 | PS_DDR_DQ54_504 | AC34 |
| PS_DDR4_DQ55 | PS_DDR_DQ55_504 | AC33 |
| PS_DDR4_DQ56 | PS_DDR_DQ56_504 | AA30 |
| PS_DDR4_DQ57 | PS_DDR_DQ57_504 | Y30 |
| PS_DDR4_DQ58 | PS_DDR_DQ58_504 | AA31 |
| PS_DDR4_DQ59 | PS_DDR_DQ59_504 | W30 |
| PS_DDR4_DQ60 | PS_DDR_DQ60_504 | Y33 |
| PS_DDR4_DQ61 | PS_DDR_DQ61_504 | W33 |
| PS_DDR4_DQ62 | PS_DDR_DQ62_504 | W34 |
| PS_DDR4_DQ63 | PS_DDR_DQ63_504 | Y34 |
| PS_DDR4_DM0 | PS_DDR_DM0_504 | AN24 |
| PS_DDR4_DM1 | PS_DDR_DM1_504 | AM29 |
| PS_DDR4_DM2 | PS_DDR_DM2_504 | AH24 |
| PS_DDR4_DM3 | PS_DDR_DM3_504 | AJ29 |
| PS_DDR4_DM4 | PS_DDR_DM4_504 | AD29 |
| PS_DDR4_DM5 | PS_DDR_DM5_504 | Y29 |
| PS_DDR4_DM6 | PS_DDR_DM6_504 | AC32 |
| PS_DDR4_DM7 | PS_DDR_DM7_504 | Y32 |
| PS_DDR4_A0 | PS_DDR_A0_504 | AN34 |
| PS_DDR4_A1 | PS_DDR_A1_504 | AM34 |
| PS_DDR4_A2 | PS_DDR_A2_504 | AM33 |
| PS_DDR4_A3 | PS_DDR_A3_504 | AL34 |
| PS_DDR4_A4 | PS_DDR_A4_504 | AL33 |
| PS_DDR4_A5 | PS_DDR_A5_504 | AK33 |
| PS_DDR4_A6 | PS_DDR_A6_504 | AK30 |
| PS_DDR4_A7 | PS_DDR_A7_504 | AJ30 |
| PS_DDR4_A8 | PS_DDR_A8_504 | AJ31 |
| PS_DDR4_A9 | PS_DDR_A9_504 | AH31 |
| PS_DDR4_A10 | PS_DDR_A10_504 | AG31 |
| PS_DDR4_A11 | PS_DDR_A11_504 | AF31 |
| PS_DDR4_A12 | PS_DDR_A12_504 | AG30 |
| PS_DDR4_A13 | PS_DDR_A13_504 | AF30 |
| PS_DDR4_ODT0 | PS_DDR_ODT0_504 | AP32 |
| PS_DDR4_PARITY | PS_DDR_PARITY_504 | AA26 |
| PS_DDR4_RAS_B | PS_DDR_A16_504 | AF28 |
| PS_DDR4_RESET_B | PS_DDR_RAM_RST_N_504 | AD26 |
| PS_DDR4_WE_B | PS_DDR_A14_504 | AG29 |
| PS_DDR4_ACT_B | PS_DDR_ACT_N_504 | AE25 |
| PS_DDR4_ALERT_B | PS_DDR_ALERT_N_504 | AB26 |
| PS_DDR4_BA0 | PS_DDR_BA0_504 | AE27 |
| PS_DDR4_BA1 | PS_DDR_BA1_504 | AE28 |
| PS_DDR4_BG0 | PS_DDR_BG0_504 | AD27 |
| PS_DDR4_CAS_B | PS_DDR_A15_504 | AG28 |
| PS_DDR4_CKE0 | PS_DDR_CKE0_504 | AN33 |
| PS_DDR4_CS0_B | PS_DDR_CS_N0_504 | AP33 |
| PS_DDR4_CLK0_N | PS_DDR_CK_N0_504 | AN32 |
| PS_DDR4_CLK0_P | PS_DDR_CK0_504 | AL31 |
Table 3.2 PS-side DDR4 SDRAM Pin Assignment
QSPI Flash
The DZ7 is equipped with two 256Mbit Quad-SPI Flash chips forming an 8-bit data bus. The Flash model is MT25QU256ABA1EW9, using 1.8V CMOS voltage standard. Due to its non-volatile nature, the QSPI Flash can be used as a boot device to store system boot images, including FPGA bitstreams, ARM application code, and other user data files. The configuration is shown in Table 4.1.
| Reference Designator | Chip Model | Capacity | Manufacturer |
| U2, U3 | MT25QU256ABA1EW9 | 256Mbit | Micron |
Table 4.1 QSPI Flash Model and Parameters
The QSPI Flash connects to the PS-side BANK500 GPIO pins, which must be configured as QSPI Flash interface in the system design.
Figure 4.1 QSPI Flash Connection Diagram
Configuration chip pin assignment:
| Signal Name | Pin Name | Pin Number |
| MIO0_QSPI0_SCLK | PS_MIO0_500 | A24 |
| MIO1_QSPI0_IO1 | PS_MIO1_500 | C24 |
| MIO2_QSPI0_IO2 | PS_MIO2_500 | B24 |
| MIO3_QSPI0_IO3 | PS_MIO3_500 | E25 |
| MIO4_QSPI0_IO0 | PS_MIO4_500 | A25 |
| MIO5_QSPI0_SS_B | PS_MIO5_500 | D25 |
| MIO7_QSPI1_SS_B | PS_MIO7_500 | B25 |
| MIO8_QSPI1_IO0 | PS_MIO8_500 | D26 |
| MIO9_QSPI1_IO1 | PS_MIO9_500 | C26 |
| MIO10_QSPI1_IO2 | PS_MIO10_500 | F26 |
| MIO11_QSPI1_IO3 | PS_MIO11_500 | B26 |
| MIO12_QSPI1_SCLK | PS_MIO12_500 | C27 |
Table 4.2 QSPI Flash Pin Assignment
eMMC Flash
The DZ7 development board is equipped with one 8GB eMMC flash chip, model MTFC8GAKAJCN-4M, supporting the JEDEC eMMC V5.0 HS-MMC interface at 1.8V or 3.3V. The eMMC connects to the Zynq with an 8-bit data width. Due to its large capacity and non-volatility, it can serve as a mass storage device for ARM applications, system files, and user data. The configuration is shown in Table 5.1.
| Reference Designator | Chip Model | Capacity | Manufacturer |
| U8 | MTFC8GAKAJCN-4M | 8GB | Micron |
Table 5.1 eMMC Flash Model and Parameters
The eMMC FLASH is connected to the GPIO of BANK500 on the PS side of the Zynq UltraScale+. In the system design, these PS-side GPIO ports must be configured to the eMMC interface function.
Figure 5.1 eMMC Flash Connection Diagram
Pin assignment of the configuration chip:
| Signal Name | Pin Name | Pin Number |
| MMC_CCLK | PS_MIO22_500 | F28 |
| MMC_CMD | PS_MIO21_500 | C28 |
| MMC_DAT0 | PS_MIO13_500 | D27 |
| MMC_DAT1 | PS_MIO14_500 | A27 |
| MMC_DAT2 | PS_MIO15_500 | E27 |
| MMC_DAT3 | PS_MIO16_500 | A28 |
| MMC_DAT4 | PS_MIO17_500 | C29 |
| MMC_DAT5 | PS_MIO18_500 | F27 |
| MMC_DAT6 | PS_MIO19_500 | B28 |
| MMC_DAT7 | PS_MIO20_500 | E29 |
| MMC_RSTN | PS_MIO23_500 | B29 |
Table 5.2 eMMC Pin Assignment
Clock Configuration
The DZ7 provides separate reference clocks and an RTC clock for the PS system and PL logic, allowing them to operate independently. The clock circuit design is shown in Figure 6.1.
Figure 6.1 Core Board Clock Sources
PS System RTC Clock
The passive crystal Y1 on the board provides a 32.768kHz RTC clock source for the PS system, connected to the PS_PADI_503 and PS_PADO_503 pins on BANK503.
| Signal Name | Pin |
| PS_PADI_503 | M25 |
| PS_PADO_503 | L25 |
Table 6.1 RTC Clock Pin Assignment
PS System Clock Source
The crystal oscillator X1 provides a 33.333MHz clock input to the PS side, connected to the PS_REF_CLK_503 pin on BANK503.
| Signal Name | Pin |
| PS_REF_CLK | R24 |
Table 6.2 PS System Clock Pin Assignment
PL System Clock Source
The board provides a differential 200MHz PL system clock source used as the reference clock for the DDR4 controller. The oscillator output connects to the PL BANK64 global clock (MRCC), which can drive the FPGA DDR4 controller and user logic.
| Signal Name | Pin |
| PL_CLK0_P | AJ9 |
| PL_CLK0_N | AK9 |
Table 6.3 PL System Clock Pin Assignment
M.2 Interface
The DZ7 is equipped with a PCIe x1 M.2 interface for connecting M.2 SSDs, with up to 5Gbps data rate. The M.2 interface uses an M-key slot supporting PCIe only (not SATA). When selecting an SSD, please choose a PCIe-compatible M.2 SSD.
The PCIe signals connect directly to the ZU7EV BANK505 MGT transceivers. One pair of TX and RX signals forms one MGT lane. The PCIe clock is provided by the Si5332 chip at 100MHz. The M.2 interface design is shown in Figure 7.1.
Figure 7.1 M.2 Interface Design
M.2 interface Zynq pin assignment:
| Signal Name | Pin Name | Pin Number | Description |
| PCIE_TX0_P | 505_TX0_P | U29 | PCIe lane 0 transmit positive |
| PCIE_TX0_N | 505_TX0_N | U30 | PCIe lane 0 transmit negative |
| PCIE_RX0_P | 505_RX0_P | U33 | PCIe lane 0 receive positive |
| PCIE_RX0_N | 505_RX0_N | U34 | PCIe lane 0 receive negative |
| PCIE_RST_N | PS_MIO37 | C33 | PCIe reset signal |
| PCIE_REFCLK_P | 505_CLK0_P | T27 | PCIe reference clock positive |
| PCIE_REFCLK_N | 505_CLK0_N | T28 | PCIe reference clock negative |
Table 7.1 M.2 Interface Pin Assignment
DP Display Interface
The DZ7 features one Mini DP output interface for video display. It supports VESA DisplayPort V1.2a, up to 4K@30Hz output, with Y-only, YCbCr444, YCbCr422, YCbCr420, and RGB video formats, and 6/8/10/12 bits per color.
The DisplayPort data lanes are driven by the ZU7EV BANK505 PS MGT transceivers. MGT lane 2 and lane 3 TX signals connect differentially to the DP connector. The DisplayPort auxiliary channel connects to PS MIO pins. The DP interface design is shown in Figure 8.1.
Figure 8.1 DP Interface Design
DisplayPort interface Zynq pin assignment:
| Signal Name | Zynq Pin Name | Zynq Pin Number | Description |
| GT0_DP_TX_N | 505_TX3_N | N30 | DP lane 0 transmit negative |
| GT0_DP_TX_P | 505_TX3_P | N29 | DP lane 0 transmit positive |
| GT1_DP_TX_N | 505_TX2_N | P32 | DP lane 1 transmit negative |
| GT1_DP_TX_P | 505_TX2_P | P31 | DP lane 1 transmit positive |
| 505_DP_CLKN | 505_CLK2_N | M32 | DP reference clock negative |
| 505_DP_CLKP | 505_CLK2_P | M31 | DP reference clock positive |
| DP_AUX_OUT_MIO27 | PS_MIO27 | A30 | DP auxiliary data output |
| DP_AUX_IN_MIO30 | PS_MIO30 | A33 | DP auxiliary data input |
| DP_OE_MIO29 | PS_MIO29 | A32 | DP auxiliary output enable |
| DP_HPD_MIO28 | PS_MIO28 | A31 | DP hot plug detect |
Table 8.1 DisplayPort Interface Pin Assignment
USB3.0 Interface
The DZ7 has one USB3.0 Type-C interface supporting HOST, SLAVE, and OTG modes, with data rates up to 5.0Gbps. USB3.0 connects via the PIPE3 interface, while USB2.0 connects through the ULPI interface to an external USB3320C PHY chip, enabling high-speed USB3.0 and USB2.0 data communication. The USB3.0 connection is shown in Figure 9.1.
Figure 9.1 USB3.0 Interface Diagram
USB interface pin assignment:
| Signal Name | Pin Name | Pin Number | Description |
| USB_SSTXN | 505_TX1_N | R30 | USB3.0 data TX negative |
| USB_SSTXP | 505_TX1_P | R29 | USB3.0 data TX positive |
| USB_SSRXN | 505_RX1_N | T32 | USB3.0 data RX negative |
| USB_SSRXP | 505_RX1_P | T31 | USB3.0 data RX positive |
| USB_DATA0 | PS_MIO56 | G34 | USB2.0 data bit 0 |
| USB_DATA1 | PS_MIO57 | H29 | USB2.0 data bit 1 |
| USB_DATA2 | PS_MIO54 | G31 | USB2.0 data bit 2 |
| USB_DATA3 | PS_MIO59 | H32 | USB2.0 data bit 3 |
| USB_DATA4 | PS_MIO60 | H33 | USB2.0 data bit 4 |
| USB_DATA5 | PS_MIO61 | H34 | USB2.0 data bit 5 |
| USB_DATA6 | PS_MIO62 | J29 | USB2.0 data bit 6 |
| USB_DATA7 | PS_MIO63 | J30 | USB2.0 data bit 7 |
| USB_STP | PS_MIO58 | H31 | USB2.0 stop signal |
| USB_DIR | PS_MIO53 | G30 | USB2.0 data direction |
| USB_CLK | PS_MIO52 | G29 | USB2.0 clock |
| USB_NXT | PS_MIO55 | G33 | USB2.0 next data |
| USB_RESET_N | PS_MIO26 | A29 | USB2.0 reset |
| PS_I2C0_SCL | PS_MIO34 | B34 | I2C clock signal |
| PS_I2C0_SDA | PS_MIO35 | C31 | I2C data signal |
Table 9.1 USB3.0 Interface Pin Assignment
Gigabit Ethernet Interface
The DZ7 has two Gigabit Ethernet interfaces connected to the PS side. The PHY chips use Microchip industrial-grade KSZ9031RNX, providing network communication for users. The PS-side Ethernet PHY chips connect to the Zynq PS BANK501 and BANK502 GPIO interfaces respectively. The KSZ9031RNX supports 10/100/1000 Mbps network rates and communicates with the Zynq MAC layer through the RGMII interface. It supports MDI/MDX auto-crossover, speed auto-negotiation, master/slave auto-negotiation, and MDIO bus for PHY register management.
The KSZ9031RNX detects specific IO levels at power-up to determine its operating mode. Table 10.1 describes the default PHY settings.
| Config Pin | Description | Configuration |
| RXD3_ADR0 / RXC_ADR1 / RXCTL_ADR2 | PHY address in MDIO/MDC mode | PHY Address = 001 |
| RXD1_TXDLY | TX clock 2ns delay | Delayed |
| RXD0_RXDLY | RX clock 2ns delay | Delayed |
Table 10.1 PHY Chip Default Configuration
When connected to a Gigabit network, the Zynq and KSZ9031RNX communicate via the RGMII bus at 125MHz clock, sampling data on both clock edges. When connected to a 100Mbps network, the RGMII clock is 25MHz, also sampling on both edges.
Figure 10.1 ZYNQ to GPHY Connection Diagram
PS Gigabit Ethernet pin assignment:
| Signal Name | Pin Name | Pin Number | Description |
| PHY1_TXCK | PS_MIO26_501 | A29 | Ethernet 1 RGMII TX clock |
| PHY1_TXD0 | PS_MIO27_501 | A30 | Ethernet 1 TX data bit 0 |
| PHY1_TXD1 | PS_MIO28_501 | A31 | Ethernet 1 TX data bit 1 |
| PHY1_TXD2 | PS_MIO29_501 | A32 | Ethernet 1 TX data bit 2 |
| PHY1_TXD3 | PS_MIO30_501 | A33 | Ethernet 1 TX data bit 3 |
| PHY1_TXCTL | PS_MIO31_501 | B30 | Ethernet 1 TX enable |
| PHY1_RXCK | PS_MIO32_501 | B31 | Ethernet 1 RGMII RX clock |
| PHY1_RXD0 | PS_MIO33_501 | B33 | Ethernet 1 RX data bit 0 |
| PHY1_RXD1 | PS_MIO34_501 | B34 | Ethernet 1 RX data bit 1 |
| PHY1_RXD2 | PS_MIO35_501 | C31 | Ethernet 1 RX data bit 2 |
| PHY1_RXD3 | PS_MIO36_501 | C32 | Ethernet 1 RX data bit 3 |
| PHY1_RXCTL | PS_MIO37_501 | C33 | Ethernet 1 RX data valid |
| PHY2_TXCK | PS_MIO64_502 | J31 | Ethernet 2 RGMII TX clock |
| PHY2_TXD0 | PS_MIO65_502 | J32 | Ethernet 2 TX data bit 0 |
| PHY2_TXD1 | PS_MIO66_502 | J34 | Ethernet 2 TX data bit 1 |
| PHY2_TXD2 | PS_MIO67_502 | K28 | Ethernet 2 TX data bit 2 |
| PHY2_TXD3 | PS_MIO68_502 | K29 | Ethernet 2 TX data bit 3 |
| PHY2_TXCTL | PS_MIO69_502 | K30 | Ethernet 2 TX enable |
| PHY2_RXCK | PS_MIO70_502 | K31 | Ethernet 2 RGMII RX clock |
| PHY2_RXD0 | PS_MIO71_502 | K32 | Ethernet 2 RX data bit 0 |
| PHY2_RXD1 | PS_MIO72_502 | K33 | Ethernet 2 RX data bit 1 |
| PHY2_RXD2 | PS_MIO73_502 | K34 | Ethernet 2 RX data bit 2 |
| PHY2_RXD3 | PS_MIO74_502 | L29 | Ethernet 2 RX data bit 3 |
| PHY2_RXCTL | PS_MIO75_502 | L30 | Ethernet 2 RX data valid |
| PHY_MDC | PS_MIO76_502 | L33 | Ethernet MDIO management clock |
| PHY_MDIO | PS_MIO77_502 | L34 | Ethernet MDIO management data |
Table 10.2 PS Gigabit Ethernet Pin Assignment
USB UART Interface
The DZ7 is equipped with one UART interface connected to the PS side, expanded through a 3-pin 2.54mm header. It can be connected to a PC USB port via a TTL-to-USB cable for serial communication. The UART circuit design is shown in Figure 11.1.
Figure 11.1 USB-to-UART Diagram
UART Zynq pin assignment:
| Signal Name | Pin Name | Pin Number | Description |
| PS_UART_RX | PS_MIO42 | D34 | PS UART data input |
| PS_UART_TX | PS_MIO43 | E30 | PS UART data output |
Table 11.1 PS UART Pin Assignment
Micro SD Card Slot
The DZ7 includes a Micro SD card slot for storing the ZU7EV boot program, Linux kernel, file system, and other user data files.
The SDIO signals connect to the ZU7EV PS BANK501 IO pins. Since the BANK501 VCCIO is set to 1.8V while the Micro SD card uses 3.3V, a TXS02612 level translator is used between them. The ZU7EV PS and Micro SD card connector schematic is shown in Figure 12.1.
Figure 12.1 SD Card Connection Diagram
Micro SD card slot pin assignment:
| Signal Name | Pin Name | Pin Number | Description |
| SD_CLK | SD_CLK | F34 | SD clock signal |
| SD_CD | SD_CD | E33 | SD card detect |
| SD_D0 | SD_D0 | E34 | SD data bit 0 |
| SD_D1 | SD_D1 | F30 | SD data bit 1 |
| SD_D2 | SD_D2 | F31 | SD data bit 2 |
| SD_D3 | SD_D3 | F32 | SD data bit 3 |
| SD_CMD | SD_CMD | F33 | SD command signal |
Table 12.1 Micro SD Card Slot Pin Assignment
QSFP+ Optical Fiber Interface
The DZ7 has a small-form-factor pluggable QSFP+ optical interface. The fiber optic transceiver integrates 4 transmit channels and 4 receive channels, providing up to 40Gbps total throughput, meeting user demands for high-density high-speed pluggable optical communication solutions.
The QSFP+ transmit and receive signals connect directly to the FPGA BANK227 GTH transceivers. All 4 TX and RX pairs connect directly to GTH channels. Since each GTX lane supports up to 10Gbps, the 4 lanes achieve up to 40Gbps. The BANK227 GTH reference clock is provided by a 156.25MHz differential oscillator. The QSFP+ control signals connect to FPGA BANK87.
Figure 13.1 QSFP+ Optical Design
QSFP+ optical interface FPGA pin assignment:
| Net Name | Pin Name | FPGA Pin | Description |
| QSFP1_TX1_P | 227_TX0_P | M4 | QSFP+ lane 1 TX positive |
| QSFP1_TX1_N | 227_TX0_N | M3 | QSFP+ lane 1 TX negative |
| QSFP1_TX2_P | 227_TX1_P | L6 | QSFP+ lane 2 TX positive |
| QSFP1_TX2_N | 227_TX1_N | L5 | QSFP+ lane 2 TX negative |
| QSFP1_TX3_P | 227_TX2_P | K4 | QSFP+ lane 3 TX positive |
| QSFP1_TX3_N | 227_TX2_N | K3 | QSFP+ lane 3 TX negative |
| QSFP1_TX4_P | 227_TX3_P | H4 | QSFP+ lane 4 TX positive |
| QSFP1_TX4_N | 227_TX3_N | H3 | QSFP+ lane 4 TX negative |
| QSFP1_RX1_P | 227_RX0_P | N2 | QSFP+ lane 1 RX positive |
| QSFP1_RX1_N | 227_RX0_N | N1 | QSFP+ lane 1 RX negative |
| QSFP1_RX2_P | 227_RX1_P | L2 | QSFP+ lane 2 RX positive |
| QSFP1_RX2_N | 227_RX1_N | L1 | QSFP+ lane 2 RX negative |
| QSFP1_RX3_P | 227_RX2_P | J2 | QSFP+ lane 3 RX positive |
| QSFP1_RX3_N | 227_RX2_N | J1 | QSFP+ lane 3 RX negative |
| QSFP1_RX4_P | 227_RX3_P | G2 | QSFP+ lane 4 RX positive |
| QSFP1_RX4_N | 227_RX3_N | G1 | QSFP+ lane 4 RX negative |
| QSFP1_MODSELL | B87_L7_P | L8 | Module select, I2C active low |
| QSFP1_RESETL | B87_L7_N | K8 | Reset, active low |
| QSFP1_INTL | B87_L8_P | K9 | Interrupt, active low |
| QSFP1_LPMODE | B87_L8_N | J9 | Low power mode select |
| QSFP1_SCL | B87_L6_N | L10 | I2C clock |
| QSFP1_SDA | B87_L6_N | M10 | I2C data |
Table 13.1 QSFP+ Optical Interface Pin Assignment
FMC Connectors
The DZ7 has two standard FMC HPC expansion connectors, allowing connection of Xilinx or Alinx FMC modules (HDMI in/out modules, binocular camera modules, high-speed AD modules, etc.). All FMC1 LA, HA, and HB bank pins are connected to FPGA pins. Due to FPGA pin limitations, not all FMC2 expansion pins are routed to the FPGA; therefore, not all FMC modules are compatible. Please evaluate module compatibility against the schematic design. The hardware connection between the two FMC connectors and the FPGA is shown in Figure 14.1.
Figure 14.1 FMC Connector Connection
FMC1 connector pin assignment is as follows:
| Pin No. | FMC Net Name | FPGA Pin Name | Pin Number |
| H5 | FMC1_CLK0_M2C_N | IO_L12N_T1U_N11_GC_64 | AJ15 |
| H4 | FMC1_CLK0_M2C_P | IO_L12P_T1U_N10_GC_64 | AJ16 |
| G3 | FMC1_CLK0_C2M_N | IO_L24N_T3U_N11_PERSTN0_65 | AA20 |
| G2 | FMC1_CLK0_C2M_P | IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 | AA19 |
| K5 | FMC1_CLK1_M2C_N | IO_L12N_T1U_N11_GC_65 | AJ22 |
| K4 | FMC1_CLK1_M2C_P | IO_L12P_T1U_N10_GC_65 | AJ21 |
| J3 | FMC1_CLK1_C2M_N | IO_L24N_T3U_N11_64 | AD16 |
| J2 | FMC1_CLK1_C2M_P | IO_L24P_T3U_N10_64 | AD17 |
| G7 | FMC1_LA00_CC_N | IO_L14N_T2L_N3_GC_64 | AG18 |
| G6 | FMC1_LA00_CC_P | IO_L14P_T2L_N2_GC_64 | AF18 |
| D9 | FMC1_LA01_CC_N | IO_L13N_T2L_N1_GC_QBC_64 | AH17 |
| D8 | FMC1_LA01_CC_P | IO_L13P_T2L_N0_GC_QBC_64 | AH18 |
| H8 | FMC1_LA02_N | IO_L15N_T2L_N5_AD11N_64 | AF17 |
| H7 | FMC1_LA02_P | IO_L15P_T2L_N4_AD11P_64 | AE17 |
| G10 | FMC1_LA03_N | IO_L18N_T2U_N11_AD2N_64 | AG14 |
| G9 | FMC1_LA03_P | IO_L18P_T2U_N10_AD2P_64 | AG15 |
| H11 | FMC1_LA04_N | IO_L17N_T2U_N9_AD10N_64 | AF15 |
| H10 | FMC1_LA04_P | IO_L17P_T2U_N8_AD10P_64 | AF16 |
| D12 | FMC1_LA05_N | IO_L16N_T2U_N7_QBC_AD3N_64 | AJ14 |
| D11 | FMC1_LA05_P | IO_L16P_T2U_N6_QBC_AD3P_64 | AH14 |
| C11 | FMC1_LA06_N | IO_L22N_T3U_N7_DBC_AD0N_64 | AA15 |
| C10 | FMC1_LA06_P | IO_L22P_T3U_N6_DBC_AD0P_64 | AA16 |
| H14 | FMC1_LA07_N | IO_L23N_T3U_N9_64 | AB14 |
| H13 | FMC1_LA07_P | IO_L23P_T3U_N8_64 | AA14 |
| G13 | FMC1_LA08_N | IO_L21N_T3L_N5_AD8N_64 | AB15 |
| G12 | FMC1_LA08_P | IO_L21P_T3L_N4_AD8P_64 | AB16 |
| D15 | FMC1_LA09_N | IO_L20N_T3L_N3_AD1N_64 | AC16 |
| D14 | FMC1_LA09_P | IO_L20P_T3L_N2_AD1P_64 | AC17 |
| C15 | FMC1_LA10_N | IO_L6N_T0U_N11_AD6N_64 | AN16 |
| C14 | FMC1_LA10_P | IO_L6P_T0U_N10_AD6P_64 | AN17 |
| H17 | FMC1_LA11_N | IO_L9N_T1L_N5_AD12N_64 | AL18 |
| H16 | FMC1_LA11_P | IO_L9P_T1L_N4_AD12P_64 | AK18 |
| G16 | FMC1_LA12_N | IO_L19N_T3L_N1_DBC_AD9N_64 | AE15 |
| G15 | FMC1_LA12_P | IO_L19P_T3L_N0_DBC_AD9P_64 | AD15 |
| D18 | FMC1_LA13_N | IO_L8N_T1L_N3_AD5N_64 | AL15 |
| D17 | FMC1_LA13_P | IO_L8P_T1L_N2_AD5P_64 | AL16 |
| C19 | FMC1_LA14_N | IO_L7N_T1L_N1_QBC_AD13N_64 | AM15 |
| C18 | FMC1_LA14_P | IO_L7P_T1L_N0_QBC_AD13P_64 | AM16 |
| H20 | FMC1_LA15_N | IO_L10N_T1U_N7_QBC_AD4N_64 | AK14 |
| H19 | FMC1_LA15_P | IO_L10P_T1U_N6_QBC_AD4P_64 | AK15 |
| G19 | FMC1_LA16_N | IO_L11N_T1U_N9_GC_64 | AK17 |
| G18 | FMC1_LA16_P | IO_L11P_T1U_N8_GC_64 | AJ17 |
| D21 | FMC1_LA17_CC_N | IO_L14N_T2L_N3_GC_65 | AH21 |
| D20 | FMC1_LA17_CC_P | IO_L14P_T2L_N2_GC_65 | AG21 |
| C23 | FMC1_LA18_CC_N | IO_L13N_T2L_N1_GC_QBC_65 | AH23 |
| C22 | FMC1_LA18_CC_P | IO_L13P_T2L_N0_GC_QBC_65 | AH22 |
| H23 | FMC1_LA19_N | IO_L18N_T2U_N11_AD2N_65 | AE24 |
| H22 | FMC1_LA19_P | IO_L18P_T2U_N10_AD2P_65 | AE23 |
| G22 | FMC1_LA20_N | IO_L16N_T2U_N7_QBC_AD3N_65 | AG23 |
| G21 | FMC1_LA20_P | IO_L16P_T2U_N6_QBC_AD3P_65 | AF23 |
| H26 | FMC1_LA21_N | IO_L21N_T3L_N5_AD8N_65 | AE20 |
| H25 | FMC1_LA21_P | IO_L21P_T3L_N4_AD8P_65 | AD20 |
| G25 | FMC1_LA22_N | IO_L20N_T3L_N3_AD1N_65 | AC19 |
| G24 | FMC1_LA22_P | IO_L20P_T3L_N2_AD1P_65 | AB19 |
| D24 | FMC1_LA23_N | IO_L22N_T3U_N7_DBC_AD0N_65 | AB18 |
| D23 | FMC1_LA23_P | IO_L22P_T3U_N6_DBC_AD0P_65 | AA18 |
| H29 | FMC1_LA24_N | IO_L17N_T2U_N9_AD10N_65 | AF22 |
| H28 | FMC1_LA24_P | IO_L17P_T2U_N8_AD10P_65 | AF21 |
| G28 | FMC1_LA25_N | IO_L6N_T0U_N11_AD6N_65 | AN23 |
| G27 | FMC1_LA25_P | IO_L6P_T0U_N10_AD6P_65 | AM23 |
| D27 | FMC1_LA26_N | IO_L19N_T3L_N1_DBC_AD9N_65 | AE19 |
| D26 | FMC1_LA26_P | IO_L19P_T3L_N0_DBC_AD9P_65 | AE18 |
| C27 | FMC1_LA27_N | IO_L23N_T3U_N9_65 | AD19 |
| C26 | FMC1_LA27_P | IO_L23P_T3U_N8_I2C_SCLK_65 | AC18 |
| H32 | FMC1_LA28_N | IO_L15N_T2L_N5_AD11N_65 | AG20 |
| H31 | FMC1_LA28_P | IO_L15P_T2L_N4_AD11P_65 | AG19 |
| G31 | FMC1_LA29_N | IO_L7N_T1L_N1_QBC_AD13N_65 | AL21 |
| G30 | FMC1_LA29_P | IO_L7P_T1L_N0_QBC_AD13P_65 | AL20 |
| H35 | FMC1_LA30_N | IO_L8N_T1L_N3_AD5N_65 | AL23 |
| H34 | FMC1_LA30_P | IO_L8P_T1L_N2_AD5P_65 | AL22 |
| G34 | FMC1_LA31_N | IO_L9N_T1L_N5_AD12N_65 | AK19 |
| G33 | FMC1_LA31_P | IO_L9P_T1L_N4_AD12P_65 | AJ19 |
| H38 | FMC1_LA32_N | IO_L10N_T1U_N7_QBC_AD4N_65 | AK23 |
| H37 | FMC1_LA32_P | IO_L10P_T1U_N6_QBC_AD4P_65 | AK22 |
| G37 | FMC1_LA33_N | IO_L11N_T1U_N9_GC_65 | AK20 |
| G36 | FMC1_LA33_P | IO_L11P_T1U_N8_GC_65 | AJ20 |
| F5 | FMC1_HA00_CC_N | IO_L14N_T2L_N3_GC_66 | AJ11 |
| F4 | FMC1_HA00_CC_P | IO_L14P_T2L_N2_GC_66 | AH11 |
| E3 | FMC1_HA01_CC_N | IO_L13N_T2L_N1_GC_QBC_66 | AJ12 |
| E2 | FMC1_HA01_CC_P | IO_L13P_T2L_N0_GC_QBC_66 | AH12 |
| K8 | FMC1_HA02_N | IO_L20N_T3L_N3_AD1N_66 | AE14 |
| K7 | FMC1_HA02_P | IO_L20P_T3L_N2_AD1P_66 | AD14 |
| J7 | FMC1_HA03_N | IO_L10N_T1U_N7_QBC_AD4N_66 | AL8 |
| J6 | FMC1_HA03_P | IO_L10P_T1U_N6_QBC_AD4P_66 | AK8 |
| F8 | FMC1_HA04_N | IO_L7N_T1L_N1_QBC_AD13N_66 | AL13 |
| F7 | FMC1_HA04_P | IO_L7P_T1L_N0_QBC_AD13P_66 | AK13 |
| E7 | FMC1_HA05_N | IO_L8N_T1L_N3_AD5N_66 | AL10 |
| E6 | FMC1_HA05_P | IO_L8P_T1L_N2_AD5P_66 | AL11 |
| K11 | FMC1_HA06_N | IO_L1N_T0L_N1_DBC_66 | AP12 |
| K10 | FMC1_HA06_P | IO_L1P_T0L_N0_DBC_66 | AN12 |
| J10 | FMC1_HA07_N | IO_L4N_T0U_N7_DBC_AD7N_66 | AN8 |
| J9 | FMC1_HA07_P | IO_L4P_T0U_N6_DBC_AD7P_66 | AN9 |
| F11 | FMC1_HA08_N | IO_L3N_T0L_N5_AD15N_66 | AP11 |
| F10 | FMC1_HA08_P | IO_L3P_T0L_N4_AD15P_66 | AN11 |
| E10 | FMC1_HA09_N | IO_L2N_T0L_N3_66 | AP9 |
| E9 | FMC1_HA09_P | IO_L2P_T0L_N2_66 | AP10 |
| K14 | FMC1_HA10_N | IO_L24N_T3U_N11_66 | AC13 |
| K13 | FMC1_HA10_P | IO_L24P_T3U_N10_66 | AB13 |
| J13 | FMC1_HA11_N | IO_L22N_T3U_N7_DBC_AD0N_66 | AD12 |
| J12 | FMC1_HA11_P | IO_L22P_T3U_N6_DBC_AD0P_66 | AC12 |
| F14 | FMC1_HA12_N | IO_L18N_T2U_N11_AD2N_66 | AG8 |
| F13 | FMC1_HA12_P | IO_L18P_T2U_N10_AD2P_66 | AF8 |
| E13 | FMC1_HA13_N | IO_L21N_T3L_N5_AD8N_66 | AF13 |
| E12 | FMC1_HA13_P | IO_L21P_T3L_N4_AD8P_66 | AE13 |
| J16 | FMC1_HA14_N | IO_L17N_T2U_N9_AD10N_66 | AG10 |
| J15 | FMC1_HA14_P | IO_L17P_T2U_N8_AD10P_66 | AG11 |
| F17 | FMC1_HA15_N | IO_L23N_T3U_N9_66 | AF12 |
| F16 | FMC1_HA15_P | IO_L23P_T3U_N8_66 | AE12 |
| E16 | FMC1_HA16_N | IO_L16N_T2U_N7_QBC_AD3N_66 | AH9 |
| E15 | FMC1_HA16_P | IO_L16P_T2U_N6_QBC_AD3P_66 | AG9 |
| K17 | FMC1_HA17_CC_N | IO_L12N_T1U_N11_GC_66 | AK9 |
| K16 | FMC1_HA17_CC_P | IO_L12P_T1U_N10_GC_66 | AJ9 |
| J19 | FMC1_HA18_N | IO_L15N_T2L_N5_AD11N_66 | AH13 |
| J18 | FMC1_HA18_P | IO_L15P_T2L_N4_AD11P_66 | AG13 |
| F20 | FMC1_HA19_N | IO_L11N_T1U_N9_GC_66 | AK10 |
| F19 | FMC1_HA19_P | IO_L11P_T1U_N8_GC_66 | AJ10 |
| E19 | FMC1_HA20_N | IO_L19N_T3L_N1_DBC_AD9N_66 | AF10 |
| E18 | FMC1_HA20_P | IO_L19P_T3L_N0_DBC_AD9P_66 | AF11 |
| K20 | FMC1_HA21_N | IO_L9N_T1L_N5_AD12N_66 | AL12 |
| K19 | FMC1_HA21_P | IO_L9P_T1L_N4_AD12P_66 | AK12 |
| J22 | FMC1_HA22_N | IO_L6N_T0U_N11_AD6N_66 | AM8 |
| J21 | FMC1_HA22_P | IO_L6P_T0U_N10_AD6P_66 | AM9 |
| K23 | FMC1_HA23_N | IO_L5N_T0U_N9_AD14N_66 | AM10 |
| K22 | FMC1_HA23_P | IO_L5P_T0U_N8_AD14P_66 | AM11 |
| K26 | FMC1_HB00_CC_N | IO_L1N_T0L_N1_DBC_65 | AP20 |
| K25 | FMC1_HB00_CC_P | IO_L1P_T0L_N0_DBC_65 | AP19 |
| J25 | FMC1_HB01_N | IO_L4N_T0U_N7_DBC_AD7N_65 | AN21 |
| J24 | FMC1_HB01_P | IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 | AM21 |
| F23 | FMC1_HB02_N | IO_L5N_T0U_N9_AD14N_65 | AP23 |
| F22 | FMC1_HB02_P | IO_L5P_T0U_N8_AD14P_65 | AN22 |
| E22 | FMC1_HB03_N | IO_L2N_T0L_N3_65 | AN19 |
| E21 | FMC1_HB03_P | IO_L2P_T0L_N2_65 | AM19 |
| F26 | FMC1_HB04_N | IO_L3N_T0L_N5_AD15N_65 | AP22 |
| F25 | FMC1_HB04_P | IO_L3P_T0L_N4_AD15P_65 | AP21 |
| E25 | FMC1_HB05_N | IO_L2N_T0L_N3_64 | AP13 |
| E24 | FMC1_HB05_P | IO_L2P_T0L_N2_64 | AN13 |
| K29 | FMC1_HB06_CC_N | IO_L5N_T0U_N9_AD14N_64 | AP15 |
| K28 | FMC1_HB06_CC_P | IO_L5P_T0U_N8_AD14P_64 | AP16 |
| J28 | FMC1_HB07_N | IO_L4N_T0U_N7_DBC_AD7N_64 | AN14 |
| J27 | FMC1_HB07_P | IO_L4P_T0U_N6_DBC_AD7P_64 | AM14 |
| F29 | FMC1_HB08_N | IO_L3N_T0L_N5_AD15N_64 | AN18 |
| F28 | FMC1_HB08_P | IO_L3P_T0L_N4_AD15P_64 | AM18 |
| E28 | FMC1_HB09_N | IO_L1N_T0L_N1_DBC_64 | AP17 |
| E27 | FMC1_HB09_P | IO_L1P_T0L_N0_DBC_64 | AP18 |
| K32 | FMC1_HB10_N | IO_L7N_HDGC_88 | B4 |
| K31 | FMC1_HB10_P | IO_L7P_HDGC_88 | C4 |
| J31 | FMC1_HB11_N | IO_L3N_AD13N_88 | A2 |
| J30 | FMC1_HB11_P | IO_L3P_AD13P_88 | A3 |
| F32 | FMC1_HB12_N | IO_L5N_HDGC_88 | C2 |
| F31 | FMC1_HB12_P | IO_L5P_HDGC_88 | D2 |
| E31 | FMC1_HB13_N | IO_L1N_AD15N_88 | D1 |
| E30 | FMC1_HB13_P | IO_L1P_AD15P_88 | E1 |
| K35 | FMC1_HB14_N | IO_L10N_AD10N_88 | A5 |
| K34 | FMC1_HB14_P | IO_L10P_AD10P_88 | B5 |
| J34 | FMC1_HB15_N | IO_L6N_HDGC_88 | B3 |
| J33 | FMC1_HB15_P | IO_L6P_HDGC_88 | C3 |
| F35 | FMC1_HB16_N | IO_L2N_AD14N_88 | B1 |
| F34 | FMC1_HB16_P | IO_L2P_AD14P_88 | C1 |
| K38 | FMC1_HB17_CC_N | IO_L8N_HDGC_88 | D4 |
| K37 | FMC1_HB17_CC_P | IO_L8P_HDGC_88 | E4 |
| J37 | FMC1_HB18_N | IO_L11N_AD9N_88 | D5 |
| J36 | FMC1_HB18_P | IO_L11P_AD9P_88 | D6 |
| E34 | FMC1_HB19_N | IO_L4N_AD12N_88 | E2 |
| E33 | FMC1_HB19_P | IO_L4P_AD12P_88 | E3 |
| F38 | FMC1_HB20_N | IO_L12N_AD8N_88 | E5 |
| F37 | FMC1_HB20_P | IO_L12P_AD8P_88 | F6 |
| E37 | FMC1_HB21_N | IO_L9N_AD11N_88 | F4 |
| E36 | FMC1_HB21_P | IO_L9P_AD11P_88 | F5 |
| C7 | FMC1_DP0_M2C_N | MGTHRXN3_224 | AE1 |
| C6 | FMC1_DP0_M2C_P | MGTHRXP3_224 | AE2 |
| A3 | FMC1_DP1_M2C_N | MGTHRXN2_224 | AF3 |
| A2 | FMC1_DP1_M2C_P | MGTHRXP2_224 | AF4 |
| A7 | FMC1_DP2_M2C_N | MGTHRXN1_224 | AG1 |
| A6 | FMC1_DP2_M2C_P | MGTHRXP1_224 | AG2 |
| A11 | FMC1_DP3_M2C_N | MGTHRXN0_224 | AJ1 |
| A10 | FMC1_DP3_M2C_P | MGTHRXP0_224 | AJ2 |
| C3 | FMC1_DP0_C2M_N | MGTHTXN3_224 | AD3 |
| C2 | FMC1_DP0_C2M_P | MGTHTXP3_224 | AD4 |
| A23 | FMC1_DP1_C2M_N | MGTHTXN2_224 | AE5 |
| A22 | FMC1_DP1_C2M_P | MGTHTXP2_224 | AE6 |
| A27 | FMC1_DP2_C2M_N | MGTHTXN0_224 | AH3 |
| A26 | FMC1_DP2_C2M_P | MGTHTXP0_224 | AH4 |
| A31 | FMC1_DP3_C2M_N | MGTHTXN1_224 | AG5 |
| A30 | FMC1_DP3_C2M_P | MGTHTXP1_224 | AG6 |
| A15 | FMC1_DP4_M2C_N | MGTHRXN0_223 | AP3 |
| A14 | FMC1_DP4_M2C_P | MGTHRXP0_223 | AP4 |
| A19 | FMC1_DP5_M2C_N | MGTHRXN1_223 | AN1 |
| A18 | FMC1_DP5_M2C_P | MGTHRXP1_223 | AN2 |
| B17 | FMC1_DP6_M2C_N | MGTHRXN2_223 | AL1 |
| B16 | FMC1_DP6_M2C_P | MGTHRXP2_223 | AL2 |
| B13 | FMC1_DP7_M2C_N | MGTHRXN3_223 | AK3 |
| B12 | FMC1_DP7_M2C_P | MGTHRXP3_223 | AK4 |
| A35 | FMC1_DP4_C2M_N | MGTHTXN1_223 | AM3 |
| A34 | FMC1_DP4_C2M_P | MGTHTXP1_223 | AM4 |
| A39 | FMC1_DP5_C2M_N | MGTHTXN0_223 | AN5 |
| A38 | FMC1_DP5_C2M_P | MGTHTXP0_223 | AN6 |
| B37 | FMC1_DP6_C2M_N | MGTHTXN2_223 | AL5 |
| B36 | FMC1_DP6_C2M_P | MGTHTXP2_223 | AL6 |
| B33 | FMC1_DP7_C2M_N | MGTHTXN3_223 | AJ5 |
| B32 | FMC1_DP7_C2M_P | MGTHTXP3_223 | AJ6 |
| D5 | FMC1_GBTCLK0_M2C_N | MGTREFCLK0N_224 | AB7 |
| D4 | FMC1_GBTCLK0_M2C_P | MGTREFCLK0P_224 | AB8 |
| B21 | FMC1_GBTCLK1_M2C_N | MGTREFCLK0N_223 | AD7 |
| B20 | FMC1_GBTCLK1_M2C_P | MGTREFCLK0P_223 | AD8 |
Table 14.1 FMC1 Connector Pin Assignment
FMC2 connector pin assignment is as follows:
| Pin No. | FMC Net Name | FPGA Pin Name | FPGA Pin Number |
| H5 | FMC2_CLK0_M2C_N | IO_L12N_T1U_N11_GC_28 | F21 |
| H4 | FMC2_CLK0_M2C_P | IO_L12P_T1U_N10_GC_28 | G21 |
| G3 | FMC2_CLK0_C2M_N | IO_L24N_T3U_N11_68 | A11 |
| G2 | FMC2_CLK0_C2M_P | IO_L24P_T3U_N10_68 | B11 |
| K5 | FMC2_CLK1_M2C_N | IO_L12N_T1U_N11_GC_68 | F10 |
| K4 | FMC2_CLK1_M2C_P | IO_L12P_T1U_N10_GC_68 | G10 |
| J3 | FMC2_CLK1_C2M_N | IO_L24N_T3U_N11_28 | B21 |
| J2 | FMC2_CLK1_C2M_P | IO_L24P_T3U_N10_28 | B20 |
| G7 | FMC2_LA00_CC_N | IO_L14N_T2L_N3_GC_28 | G24 |
| G6 | FMC2_LA00_CC_P | IO_L14P_T2L_N2_GC_28 | G23 |
| D9 | FMC2_LA01_CC_N | IO_L13N_T2L_N1_GC_QBC_28 | E23 |
| D8 | FMC2_LA01_CC_P | IO_L13P_T2L_N0_GC_QBC_28 | F23 |
| H8 | FMC2_LA02_N | IO_L16N_T2U_N7_QBC_AD3N_28 | D24 |
| H7 | FMC2_LA02_P | IO_L16P_T2U_N6_QBC_AD3P_28 | E24 |
| G10 | FMC2_LA03_N | IO_L18N_T2U_N11_AD2N_28 | G26 |
| G9 | FMC2_LA03_P | IO_L18P_T2U_N10_AD2P_28 | G25 |
| H11 | FMC2_LA04_N | IO_L15N_T2L_N5_AD11N_28 | C22 |
| H10 | FMC2_LA04_P | IO_L15P_T2L_N4_AD11P_28 | C21 |
| D12 | FMC2_LA05_N | IO_L17N_T2U_N9_AD10N_28 | C23 |
| D11 | FMC2_LA05_P | IO_L17P_T2U_N8_AD10P_28 | D22 |
| C11 | FMC2_LA06_N | IO_L23N_T3U_N9_28 | A23 |
| C10 | FMC2_LA06_P | IO_L23P_T3U_N8_28 | A22 |
| H14 | FMC2_LA07_N | IO_L22N_T3U_N7_DBC_AD0N_28 | B19 |
| H13 | FMC2_LA07_P | IO_L22P_T3U_N6_DBC_AD0P_28 | B18 |
| G13 | FMC2_LA08_N | IO_L21N_T3L_N5_AD8N_28 | A21 |
| G12 | FMC2_LA08_P | IO_L21P_T3L_N4_AD8P_28 | A20 |
| D15 | FMC2_LA09_N | IO_L20N_T3L_N3_AD1N_28 | C19 |
| D14 | FMC2_LA09_P | IO_L20P_T3L_N2_AD1P_28 | C18 |
| C15 | FMC2_LA10_N | IO_L6N_T0U_N11_AD6N_28 | H24 |
| C14 | FMC2_LA10_P | IO_L6P_T0U_N10_AD6P_28 | J24 |
| H17 | FMC2_LA11_N | IO_L9N_T1L_N5_AD12N_28 | D21 |
| H16 | FMC2_LA11_P | IO_L9P_T1L_N4_AD12P_28 | D20 |
| G16 | FMC2_LA12_N | IO_L19N_T3L_N1_DBC_AD9N_28 | A19 |
| G15 | FMC2_LA12_P | IO_L19P_T3L_N0_DBC_AD9P_28 | A18 |
| D18 | FMC2_LA13_N | IO_L8N_T1L_N3_AD5N_28 | H22 |
| D17 | FMC2_LA13_P | IO_L8P_T1L_N2_AD5P_28 | H21 |
| C19 | FMC2_LA14_N | IO_L7N_T1L_N1_QBC_AD13N_28 | D19 |
| C18 | FMC2_LA14_P | IO_L7P_T1L_N0_QBC_AD13P_28 | E19 |
| H20 | FMC2_LA15_N | IO_L10N_T1U_N7_QBC_AD4N_28 | F20 |
| H19 | FMC2_LA15_P | IO_L10P_T1U_N6_QBC_AD4P_28 | G20 |
| G19 | FMC2_LA16_N | IO_L11N_T1U_N9_GC_28 | E22 |
| G18 | FMC2_LA16_P | IO_L11P_T1U_N8_GC_28 | F22 |
| D21 | FMC2_LA17_CC_N | IO_L14N_T2L_N3_GC_68 | E10 |
| D20 | FMC2_LA17_CC_P | IO_L14P_T2L_N2_GC_68 | F11 |
| C23 | FMC2_LA18_CC_N | IO_L13N_T2L_N1_GC_QBC_68 | G11 |
| C22 | FMC2_LA18_CC_P | IO_L13P_T2L_N0_GC_QBC_68 | H11 |
| H23 | FMC2_LA19_N | IO_L18N_T2U_N11_AD2N_68 | C11 |
| H22 | FMC2_LA19_P | IO_L18P_T2U_N10_AD2P_68 | D12 |
| G22 | FMC2_LA20_N | IO_L17N_T2U_N9_AD10N_68 | E12 |
| G21 | FMC2_LA20_P | IO_L17P_T2U_N8_AD10P_68 | F12 |
| H26 | FMC2_LA21_N | IO_L10N_T1U_N7_QBC_AD4N_68 | D9 |
| H25 | FMC2_LA21_P | IO_L10P_T1U_N6_QBC_AD4P_68 | E9 |
| G25 | FMC2_LA22_N | IO_L11N_T1U_N9_GC_68 | G9 |
| G24 | FMC2_LA22_P | IO_L11P_T1U_N8_GC_68 | H9 |
| D24 | FMC2_LA23_N | IO_L9N_T1L_N5_AD12N_68 | E8 |
| D23 | FMC2_LA23_P | IO_L9P_T1L_N4_AD12P_68 | F8 |
| H29 | FMC2_LA24_N | IO_L16N_T2U_N7_QBC_AD3N_68 | D10 |
| H28 | FMC2_LA24_P | IO_L16P_T2U_N6_QBC_AD3P_68 | D11 |
| G28 | FMC2_LA25_N | IO_L6N_T0U_N11_AD6N_68 | K13 |
| G27 | FMC2_LA25_P | IO_L6P_T0U_N10_AD6P_68 | L14 |
| D27 | FMC2_LA26_N | IO_L7N_T1L_N1_QBC_AD13N_68 | E7 |
| D26 | FMC2_LA26_P | IO_L7P_T1L_N0_QBC_AD13P_68 | F7 |
| C27 | FMC2_LA27_N | IO_L8N_T1L_N3_AD5N_68 | C8 |
| C26 | FMC2_LA27_P | IO_L8P_T1L_N2_AD5P_68 | C9 |
| H32 | FMC2_LA28_N | IO_L15N_T2L_N5_AD11N_68 | H12 |
| H31 | FMC2_LA28_P | IO_L15P_T2L_N4_AD11P_68 | H13 |
| G31 | FMC2_LA29_N | IO_L1N_T0L_N1_DBC_68 | L13 |
| G30 | FMC2_LA29_P | IO_L1P_T0L_N0_DBC_68 | M13 |
| H35 | FMC2_LA30_N | IO_L4N_T0U_N7_DBC_AD7N_68 | J11 |
| H34 | FMC2_LA30_P | IO_L4P_T0U_N6_DBC_AD7P_68 | K12 |
| G34 | FMC2_LA31_N | IO_L5N_T0U_N9_AD14N_68 | J14 |
| G33 | FMC2_LA31_P | IO_L5P_T0U_N8_AD14P_68 | K14 |
| H38 | FMC2_LA32_N | IO_L3N_T0L_N5_AD15N_68 | L11 |
| H37 | FMC2_LA32_P | IO_L3P_T0L_N4_AD15P_68 | L12 |
| G37 | FMC2_LA33_N | IO_L2N_T0L_N3_68 | J10 |
| G36 | FMC2_LA33_P | IO_L2P_T0L_N2_68 | K10 |
| F5 | FMC2_HA00_CC_N | IO_L13N_T2L_N1_GC_QBC_67 | F16 |
| F4 | FMC2_HA00_CC_P | IO_L13P_T2L_N0_GC_QBC_67 | F17 |
| E3 | FMC2_HA01_CC_N | IO_L14N_T2L_N3_GC_67 | F15 |
| E2 | FMC2_HA01_CC_P | IO_L14P_T2L_N2_GC_67 | G15 |
| K8 | FMC2_HA02_N | IO_L8N_T1L_N3_AD5N_67 | C17 |
| K7 | FMC2_HA02_P | IO_L8P_T1L_N2_AD5P_67 | D17 |
| J7 | FMC2_HA03_N | IO_L19N_T3L_N1_DBC_AD9N_67 | K20 |
| J6 | FMC2_HA03_P | IO_L19P_T3L_N0_DBC_AD9P_67 | L20 |
| F8 | FMC2_HA04_N | IO_L17N_T2U_N9_AD10N_67 | F18 |
| F7 | FMC2_HA04_P | IO_L17P_T2U_N8_AD10P_67 | G18 |
| E7 | FMC2_HA05_N | IO_L15N_T2L_N5_AD11N_67 | G19 |
| E6 | FMC2_HA05_P | IO_L15P_T2L_N4_AD11P_67 | H19 |
| K11 | FMC2_HA06_N | IO_L6N_T0U_N11_AD6N_67 | C12 |
| K10 | FMC2_HA06_P | IO_L6P_T0U_N10_AD6P_67 | C13 |
| J10 | FMC2_HA07_N | IO_L20N_T3L_N3_AD1N_67 | J15 |
| J9 | FMC2_HA07_P | IO_L20P_T3L_N2_AD1P_67 | J16 |
| F11 | FMC2_HA08_N | IO_L7N_T1L_N1_QBC_AD13N_67 | C16 |
| F10 | FMC2_HA08_P | IO_L7P_T1L_N0_QBC_AD13P_67 | D16 |
| E10 | FMC2_HA09_N | IO_L18N_T2U_N11_AD2N_67 | G16 |
| E9 | FMC2_HA09_P | IO_L18P_T2U_N10_AD2P_67 | H16 |
| K14 | FMC2_HA10_N | IO_L24N_T3U_N11_67 | L16 |
| K13 | FMC2_HA10_P | IO_L24P_T3U_N10_67 | L17 |
| J13 | FMC2_HA11_N | IO_L21N_T3L_N5_AD8N_67 | J17 |
| J12 | FMC2_HA11_P | IO_L21P_T3L_N4_AD8P_67 | K17 |
| F14 | FMC2_HA12_N | IO_L5N_T0U_N9_AD14N_67 | A12 |
| F13 | FMC2_HA12_P | IO_L5P_T0U_N8_AD14P_67 | A13 |
| E13 | FMC2_HA13_N | IO_L10N_T1U_N7_QBC_AD4N_67 | F13 |
| E12 | FMC2_HA13_P | IO_L10P_T1U_N6_QBC_AD4P_67 | G14 |
| J16 | FMC2_HA14_N | IO_T2U_N12_67 | J19 |
| J15 | FMC2_HA14_P | IO_T3U_N12_67 | J20 |
| F17 | FMC2_HA15_N | IO_L23N_T3U_N9_67 | K18 |
| F16 | FMC2_HA15_P | IO_L23P_T3U_N8_67 | K19 |
| E16 | FMC2_HA16_N | IO_L22N_T3U_N7_DBC_AD0N_67 | K15 |
| E15 | FMC2_HA16_P | IO_L22P_T3U_N6_DBC_AD0P_67 | L15 |
| K17 | FMC2_HA17_CC_N | IO_L12N_T1U_N11_GC_67 | E14 |
| K16 | FMC2_HA17_CC_P | IO_L12P_T1U_N10_GC_67 | E15 |
| J19 | FMC2_HA18_N | IO_L9N_T1L_N5_AD12N_67 | E17 |
| J18 | FMC2_HA18_P | IO_L9P_T1L_N4_AD12P_67 | E18 |
| F20 | FMC2_HA19_N | IO_L1N_T0L_N1_DBC_67 | A16 |
| F19 | FMC2_HA19_P | IO_L1P_T0L_N0_DBC_67 | A17 |
| E19 | FMC2_HA20_N | IO_L16N_T2U_N7_QBC_AD3N_67 | H17 |
| E18 | FMC2_HA20_P | IO_L16P_T2U_N6_QBC_AD3P_67 | H18 |
| K20 | FMC2_HA21_N | IO_L2N_T0L_N3_67 | B15 |
| K19 | FMC2_HA21_P | IO_L2P_T0L_N2_67 | B16 |
| J22 | FMC2_HA22_N | IO_L3N_T0L_N5_AD15N_67 | A14 |
| J21 | FMC2_HA22_P | IO_L3P_T0L_N4_AD15P_67 | A15 |
| K23 | FMC2_HA23_N | IO_L4N_T0U_N7_DBC_AD7N_67 | B13 |
| K22 | FMC2_HA23_P | IO_L4P_T0U_N6_DBC_AD7P_67 | B14 |
| K26 | FMC2_HB00_CC_N | IO_L1N_T0L_N1_DBC_28 | L22 |
| K25 | FMC2_HB00_CC_P | IO_L1P_T0L_N0_DBC_28 | L21 |
| J25 | FMC2_HB01_N | IO_L2N_T0L_N3_28 | K24 |
| J24 | FMC2_HB01_P | IO_L2P_T0L_N2_28 | L23 |
| F23 | FMC2_HB02_N | IO_L4N_T0U_N7_DBC_AD7N_28 | K23 |
| F22 | FMC2_HB02_P | IO_L4P_T0U_N6_DBC_AD7P_28 | K22 |
| E22 | FMC2_HB03_N | IO_L3N_T0L_N5_AD15N_28 | J22 |
| E21 | FMC2_HB03_P | IO_L3P_T0L_N4_AD15P_28 | J21 |
| F26 | FMC2_HB04_N | IO_L5N_T0U_N9_AD14N_28 | H26 |
| F25 | FMC2_HB04_P | IO_L5P_T0U_N8_AD14P_28 | J25 |
| E25 | FMC2_HB05_N | IO_L22N_T3U_N7_DBC_AD0N_68 | A10 |
| E24 | FMC2_HB05_P | IO_L22P_T3U_N6_DBC_AD0P_68 | B10 |
| K29 | FMC2_HB06_CC_N | IO_L20N_T3L_N3_AD1N_68 | B8 |
| K28 | FMC2_HB06_CC_P | IO_L20P_T3L_N2_AD1P_68 | B9 |
| J28 | FMC2_HB07_N | IO_L21N_T3L_N5_AD8N_68 | A6 |
| J27 | FMC2_HB07_P | IO_L21P_T3L_N4_AD8P_68 | B6 |
| F29 | FMC2_HB08_N | IO_L23N_T3U_N9_68 | A7 |
| F28 | FMC2_HB08_P | IO_L23P_T3U_N8_68 | A8 |
| E28 | FMC2_HB09_N | IO_L19N_T3L_N1_DBC_AD9N_68 | C6 |
| E27 | FMC2_HB09_P | IO_L19P_T3L_N0_DBC_AD9P_68 | C7 |
| C7 | FMC2_DP0_M2C_N | MGTHRXN0_226 | V3 |
| C6 | FMC2_DP0_M2C_P | MGTHRXP0_226 | V4 |
| A3 | FMC2_DP1_M2C_N | MGTHRXN1_226 | U1 |
| A2 | FMC2_DP1_M2C_P | MGTHRXP1_226 | U2 |
| A7 | FMC2_DP2_M2C_N | MGTHRXN2_226 | R1 |
| A6 | FMC2_DP2_M2C_P | MGTHRXP2_226 | R2 |
| A11 | FMC2_DP3_M2C_N | MGTHRXN3_226 | P3 |
| A10 | FMC2_DP3_M2C_P | MGTHRXP3_226 | P4 |
| C3 | FMC2_DP0_C2M_N | MGTHTXN0_226 | U5 |
| C2 | FMC2_DP0_C2M_P | MGTHTXP0_226 | U6 |
| A23 | FMC2_DP1_C2M_N | MGTHTXN1_226 | T3 |
| A22 | FMC2_DP1_C2M_P | MGTHTXP1_226 | T4 |
| A27 | FMC2_DP2_C2M_N | MGTHTXN2_226 | R5 |
| A26 | FMC2_DP2_C2M_P | MGTHTXP2_226 | R6 |
| A31 | FMC2_DP3_C2M_N | MGTHTXN3_226 | N5 |
| A30 | FMC2_DP3_C2M_P | MGTHTXP3_226 | N6 |
| A15 | FMC2_DP4_M2C_N | MGTHRXN0_225 | AC1 |
| A14 | FMC2_DP4_M2C_P | MGTHRXP0_225 | AC2 |
| A19 | FMC2_DP5_M2C_N | MGTHRXN1_225 | AB3 |
| A18 | FMC2_DP5_M2C_P | MGTHRXP1_225 | AB4 |
| B17 | FMC2_DP6_M2C_N | MGTHRXN2_225 | AA1 |
| B16 | FMC2_DP6_M2C_P | MGTHRXP2_225 | AA2 |
| B13 | FMC2_DP7_M2C_N | MGTHRXN3_225 | W1 |
| B12 | FMC2_DP7_M2C_P | MGTHRXP3_225 | W2 |
| A35 | FMC2_DP4_C2M_N | MGTHTXN0_225 | AC5 |
| A34 | FMC2_DP4_C2M_P | MGTHTXP0_225 | AC6 |
| A39 | FMC2_DP5_C2M_N | MGTHTXN1_225 | AA5 |
| A38 | FMC2_DP5_C2M_P | MGTHTXP1_225 | AA6 |
| B37 | FMC2_DP6_C2M_N | MGTHTXN2_225 | Y3 |
| B36 | FMC2_DP6_C2M_P | MGTHTXP2_225 | Y4 |
| B33 | FMC2_DP7_C2M_N | MGTHTXN3_225 | W5 |
| B32 | FMC2_DP7_C2M_P | MGTHTXP3_225 | W6 |
| D5 | FMC2_GBTCLK0_M2C_N | MGTREFCLK0N_226 | V7 |
| D4 | FMC2_GBTCLK0_M2C_P | MGTREFCLK0P_226 | V8 |
| B21 | FMC2_GBTCLK1_M2C_N | MGTREFCLK0N_225 | Y7 |
| B20 | FMC2_GBTCLK1_M2C_P | MGTREFCLK0P_225 | Y8 |
Table 14.2 FMC2 Connector Pin Assignment
JTAG Debug Port
The DZ7 provides a JTAG interface for downloading Zynq UltraScale+ programs or programming them into Flash. To prevent damage to the Zynq chip from hot-plugging, protection diodes are added on the JTAG signals to keep signal voltages within the FPGA acceptable range.
EEPROM
The DZ7 has one EEPROM chip, model 24LC04, with a capacity of 4Kbit (256 x 8 bits). It communicates with the PS side via the I2C bus, connected to the Zynq UltraScale+ BANK501 MIO. The EEPROM schematic is shown in Figure 16.1.
Figure 16.1 EEPROM Schematic
I2C communication pin assignment:
| Signal Name | Pin Name | Pin Number | Description |
| PS_I2C0_SCL | PS_MIO34 | C34 | I2C clock signal |
| PS_I2C0_SDA | PS_MIO35 | D30 | I2C data signal |
Table 16.1 I2C Bus Pin Assignment
CANFD and GPS Interface
The DZ7 has 2 CAN communication channels connected to the PL BANK87 GPIO. The CAN transceiver chips use NXP TJA1051T/3 to provide CAN communication. GPS signals are connected to the PL BANK87 GPIO through a level shifter. Figure 17.1 shows the PL-side CAN transceiver and GPS signal connections.
Figure 17.1 PL-side CAN Transceiver and GPS Connections
CAN communication and GPS pin assignment:
| Signal Name | Pin Name | Pin Number | Description |
| CANFD1_TXD | B87_L2_N | N8 | CAN1 transmit |
| CANFD1_RXD | B87_L2_P | N9 | CAN1 receive |
| CANFD2_TXD | B87_L1N | N12 | CAN2 transmit |
| CANFD2_RXD | B87_L1_P | P12 | CAN2 receive |
| GPS_UART_TX | B87_L3_N | M12 | GPS data transmit |
| GPS_UART_RX | B87_L3_P | N13 | GPS data receive |
| GPS_PPS_IN | B87_L4_N | M11 | GPS time synchronization |
| GPS_TRIG_OUT | B87_L4_P | N11 | GPS trigger signal |
Table 17.1 CAN and GPS Pin Assignment
LEDs
The DZ7 has 4 LEDs and 1 dual-color LED. This includes 1 power indicator, 1 DONE indicator, 1 dual-color LED controlled by PS, and 2 user LEDs. Users can control LEDs on/off through software. The user LED hardware connection is shown in Figure 18.1.
Figure 18.1 User LED Hardware Connection
User LED pin assignment:
| Signal Name | Pin Name | Pin Number | Description |
| PS_LED1 | PS_MIO44 | D31 | User PS LED 1 |
| PS_LED2 | PS_MIO38 | D32 | User PS LED 2 |
Table 18.1 User LED Pin Assignment
Button
The DZ7 has 1 reset button. The reset signal connects to the PS MIO, allowing users to reset the Zynq system. The reset button is active low. The reset button connection is shown in Figure 19.1.
Figure 19.1 Reset Button Connection
Button Zynq pin assignment
| Signal Name | Pin Name | Pin Number | Description |
| SYS_RESET | PS_MIO6 | A26 | PS button input |
Table 19.1 Reset Button Pin Assignment
DIP Switch Configuration
The board has a 4-bit DIP switch SW1 used to configure the Zynq system boot mode. The DZ7 platform supports 4 boot modes: JTAG debug mode, QSPI Flash boot, eMMC boot, and SD 2.0 card boot. After power-up, the ZU7EV chip detects the PS_MODE0~3 pin levels to determine the boot mode. Users can select different boot modes via the DIP switch SW1. The SW1 boot mode configuration is shown in Table 20.1.
| SW1 | DIP Switch Position (1,2,3,4) | MODE[3:0] | Boot Mode |
| ON, ON, ON, ON | 0000 | PS JTAG |
| ON, ON, OFF, ON | 0010 | QSPI Flash | |
| ON, OFF, ON, OFF | 0101 | SD Card | |
| ON, OFF, OFF, ON | 0110 | eMMC |
Table 20.1 SW1 Boot Mode Configuration
Power Supply
The DZ7 requires a DC 12V power input. The carrier board uses 4 DC/DC power supply chips to generate +5V, QSFP_3.3V, +1.8V, and FMC_VADJ. The board power design is shown in Figure 21.1.
Figure 21.1 Power Supply Schematic
Additionally, the board uses a PMIC chip TPS6508640 to generate all other power rails required by the XCZU7EV chip. Please refer to the power chip datasheet for TPS6508640 design details. The power block diagram is shown in Figure 21.2.
Figure 21.2 TPS6508640 Power Block Diagram
The function of each power rail is shown in the following table:
| Power Rail | Function |
| +5.0V | USB power supply |
| +1.8V | Ethernet, USB power supply |
| QSFP_+3.3V | QSFP power supply |
| FMC_VADJ | FMC, FPGA bank voltage |
Table 21.1 Power Distribution
Fan
Since the ZU7EV generates significant heat during normal operation, a heatsink and fan are installed on the board to prevent overheating. The fan is controlled by the Zynq chip via BANK68 IO pin D7. When the IO outputs low, the MOSFET turns on and the fan runs; when the IO outputs high, the fan stops. The fan is pre-installed on the board. The fan power connects to the J11 header, with red wire as positive and black wire as negative.
Mechanical Dimensions
The DZ7 development board measures 230mm x 160mm. Please refer to Figure 23.1 for the top view with dimension markings.
Figure 23.1 Top View
Appendix: List of Abbreviations
| Abbreviation | Full English Name | Description |
| PS | Processor System | The processing subsystem in an SoC, typically including CPU cores, memory controllers, and peripheral interfaces. |
| PL | Programmable Logic | User-configurable FPGA logic resources for implementing custom digital circuits and hardware acceleration. |
| SoC | System on Chip | An integrated circuit combining processors, memory controllers, and peripheral interfaces on a single chip. |
| DDR4 | Double Data Rate 4 SDRAM | Fourth-generation synchronous dynamic memory technology transferring data on both clock edges. |
| eMMC | Embedded Multi Media Card | An embedded non-volatile storage device integrating NAND Flash and a controller in one package. |
| QSPI | Quad Serial Peripheral Interface | A high-speed serial interface using four data lines, commonly used for NOR Flash boot devices. |
| GTH | Gigabit Transceiver | High-speed serial transceivers in Xilinx FPGAs supporting multi-gigabit data rates. |
| UART | Universal Asynchronous Receiver/Transmitter | An asynchronous serial communication interface using TX and RX lines. |
| DP | DisplayPort | A digital display interface standard for video and audio transmission. |
| PCIe | Peripheral Component Interconnect Express | A high-speed serial expansion bus standard. |
| USB | Universal Serial Bus | A standard serial interface for data communication and power delivery. |
| JTAG | Joint Test Action Group | A standardized interface for device testing, boundary scan, and FPGA programming. |
| QSFP+ | Quad Small Form-factor Pluggable Plus | A high-density hot-pluggable optical transceiver supporting up to 40Gbps. |
| MIO | Multiplexed I/O | Multiplexed processor I/O pins configurable as UART, I2C, SPI, or GPIO. |
| PHY | Physical Layer Transceiver | An analog front-end device that converts digital data to/from physical network signals. |
| I2C | Inter-Integrated Circuit | A two-wire serial bus using SDA and SCL for connecting peripherals. |
| RGMII | Reduced Gigabit Media Independent Interface | A reduced-pin-count Ethernet MAC-to-PHY interface supporting up to 1000Mbps. |
| FMC | FPGA Mezzanine Card | A standard mezzanine connector for FPGA I/O expansion. |
| LED | Light Emitting Diode | A semiconductor device that emits light, used for status indication. |
| CANFD | Controller Area Network Flexible Data Rate | An upgraded CAN bus standard supporting flexible data rates up to 5Mbps. |
| GPS | Global Positioning System | A satellite-based navigation system providing location and time synchronization. |
| EEPROM | Electrically Erasable Programmable Read-Only Memory | A non-volatile memory that can be erased and rewritten electrically. |
| DDR | Double Data Rate | Memory technology transferring data on both rising and falling clock edges. |
| PMIC | Power Management IC | A chip that integrates multiple power conversion and management functions. |
Contact information
Alinx Electronic Limited
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Service Hotline: +86 21 67676997
Technical Support:technical@alinx.com